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Merge remote-tracking branch 'origin' into tech_reorg

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This commit is contained in:
Matt Guthaus
2019-03-08 08:33:46 -08:00
parent d8f64500e6 e39f9ee481
commit 7129f79dc4
7 changed files with 88 additions and 43 deletions
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compiler/tests/21_hspice_delay_test.py
+2 -10
View File
@@ -51,9 +51,7 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_bl': [0.1980959],
'delay_br': [0.1946091],
'delay_hl': [0.2121267],
golden_data = {'delay_hl': [0.2121267],
'delay_lh': [0.2121267],
'leakage_power': 0.0023761999999999998,
'min_period': 0.43,
@@ -61,14 +59,10 @@ class timing_sram_test(openram_test):
'read1_power': [0.48940979999999995],
'slew_hl': [0.0516745],
'slew_lh': [0.0516745],
'volt_bl': [0.5374525],
'volt_br': [1.1058],
'write0_power': [0.46267169999999996],
'write1_power': [0.4670826]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_bl': [1.1029],
'delay_br': [0.9656455999999999],
'delay_hl': [1.288],
golden_data = {'delay_hl': [1.288],
'delay_lh': [1.288],
'leakage_power': 0.0273896,
'min_period': 2.578,
@@ -76,8 +70,6 @@ class timing_sram_test(openram_test):
'read1_power': [16.2616],
'slew_hl': [0.47891700000000004],
'slew_lh': [0.47891700000000004],
'volt_bl': [4.2155],
'volt_br': [5.8142],
'write0_power': [16.0656],
'write1_power': [16.2616]}
compiler/tests/21_ngspice_delay_test.py
+2 -10
View File
@@ -51,9 +51,7 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_bl': [0.2003652],
'delay_br': [0.198698],
'delay_hl': [0.2108836],
golden_data = {'delay_hl': [0.2108836],
'delay_lh': [0.2108836],
'leakage_power': 0.001564799,
'min_period': 0.508,
@@ -61,14 +59,10 @@ class timing_sram_test(openram_test):
'read1_power': [0.4198608],
'slew_hl': [0.0455126],
'slew_lh': [0.0455126],
'volt_bl': [0.6472883],
'volt_br': [1.114024],
'write0_power': [0.40681890000000004],
'write1_power': [0.4198608]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_bl': [1.3937359999999999],
'delay_br': [1.2596429999999998],
'delay_hl': [1.5747600000000002],
golden_data = {'delay_hl': [1.5747600000000002],
'delay_lh': [1.5747600000000002],
'leakage_power': 0.00195795,
'min_period': 3.281,
@@ -76,8 +70,6 @@ class timing_sram_test(openram_test):
'read1_power': [14.369810000000001],
'slew_hl': [0.49631959999999997],
'slew_lh': [0.49631959999999997],
'volt_bl': [4.132618],
'volt_br': [5.573099],
'write0_power': [13.79953],
'write1_power': [14.369810000000001]}