From 7038fad9301e3229364feb084233bb074cafdd91 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Sun, 9 Feb 2020 23:10:33 -0800 Subject: [PATCH] s8 gdsless netlist only working up to pdriver --- compiler/modules/custom_module_properties.py | 27 ++++++++++++++++++++ compiler/modules/dff_buf.py | 9 +++++-- compiler/modules/dff_buf_array.py | 14 +++++++--- 3 files changed, 45 insertions(+), 5 deletions(-) diff --git a/compiler/modules/custom_module_properties.py b/compiler/modules/custom_module_properties.py index e27741ea..768a8c18 100644 --- a/compiler/modules/custom_module_properties.py +++ b/compiler/modules/custom_module_properties.py @@ -13,17 +13,44 @@ class _dff: self.custom_type_list = custom_type_list self.clk_pin = clk_pin +class _dff_buff: + def __init__(self, use_custom_ports, custom_buff_ports, add_body_contacts): + self.use_custom_ports = use_custom_ports + self.buf_ports = custom_buff_ports + self.add_body_contacts = add_body_contacts + +class _dff_buff_array: + def __init__(self, use_custom_ports, add_body_contacts): + self.use_custom_ports = use_custom_ports + self.add_body_contacts = add_body_contacts + class module_properties(): """ TODO """ def __init__(self): self.names = {} + self._dff = _dff(use_custom_ports = False, custom_port_list = ["D", "Q", "clk", "vdd", "gnd"], custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"], clk_pin= "clk") + + self._dff_buff = _dff_buff(use_custom_ports = False, + custom_buff_ports = ["D", "qint", "clk", "vdd", "gnd"], + add_body_contacts = False) + + self._dff_buff_array = _dff_buff_array(use_custom_ports = False, + add_body_contacts = False) @property def dff(self): return self._dff + + @property + def dff_buff(self): + return self._dff_buff + + @property + def dff_buff_array(self): + return self._dff_buff_array \ No newline at end of file diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 9e2ff0aa..d2698b34 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -7,7 +7,7 @@ # import debug import design -from tech import drc,parameter +from tech import drc,parameter,module_properties from math import log from vector import vector from globals import OPTS @@ -82,10 +82,15 @@ class dff_buf(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") + if module_properties.dff_buff.add_body_contacts: + self.add_pin("vpb", "INPUT") + self.add_pin("vpn", "INPUT") + def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) + self.connect_inst(module_properties.dff_buff.buf_ports) + #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", mod=self.inv1) diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 8b8e21dc..326fdda1 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -7,7 +7,7 @@ # import debug import design -from tech import drc +from tech import drc, module_properties from math import log from vector import vector from globals import OPTS @@ -64,6 +64,10 @@ class dff_buf_array(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") + if module_properties.dff_buff_array.add_body_contacts: + self.add_pin("vpb", "INPUT") + self.add_pin("vnb", "INPUT") + def add_modules(self): self.dff = factory.create(module_type="dff_buf", inv1_size=self.inv1_size, @@ -77,12 +81,16 @@ class dff_buf_array(design.design): name = "dff_r{0}_c{1}".format(row,col) self.dff_insts[row,col]=self.add_inst(name=name, mod=self.dff) - self.connect_inst([self.get_din_name(row,col), + inst_ports = [self.get_din_name(row,col), self.get_dout_name(row,col), self.get_dout_bar_name(row,col), "clk", "vdd", - "gnd"]) + "gnd"] + if module_properties.dff_buff_array.add_body_contacts: + inst_ports.append("vpb") + inst_ports.append("vnb") + self.connect_inst(inst_ports) def place_dff_array(self): for row in range(self.rows):