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fix

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Jesse Cirimelli-Low
2023-07-28 21:46:07 -07:00
parent 8d8f243f99
commit 6f9618f28a
3 changed files with 16 additions and 8 deletions
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compiler/tests/05_bitcell_array_test.py
+1 -1
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@@ -31,7 +31,7 @@ class array_test(openram_test):
num_spare_rows = 0
num_spare_cols = 0
a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows)
a = factory.create(module_type="bitcell_array", cols=4 + num_spare_cols, rows=2 + num_spare_rows)
self.local_check(a)
openram.end_openram()