From 6f9618f28aa62d0157f3f2dff70029b8dc42dd43 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 28 Jul 2023 21:46:07 -0700 Subject: [PATCH] fix --- compiler/modules/bitcell_array.py | 4 ++-- compiler/modules/pattern.py | 18 +++++++++++++----- compiler/tests/05_bitcell_array_test.py | 2 +- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index f95cde51..4400a508 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -64,8 +64,8 @@ class bitcell_array(bitcell_base_array): core_block[0][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True) core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True) core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, is_bitcell=True) - core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True) - self.pattern = pattern(self, "bitcell_array", core_block, self.row_size, self.column_size) + core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True) + self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size) self.pattern.connect_array() def analytical_power(self, corner, load): diff --git a/compiler/modules/pattern.py b/compiler/modules/pattern.py index bce6763d..369f8fa4 100644 --- a/compiler/modules/pattern.py +++ b/compiler/modules/pattern.py @@ -49,8 +49,10 @@ class pattern(): self.num_cores_y = num_cores_y if num_cores_x == 0: self.num_cores_x = ceil(num_cols/len(core_block[0])) + print('num_cores_x:', self.num_cores_x) if num_cores_y == 0: - self.num_cores_y = ceil(num_rows/len(core_block)) + self.num_cores_y = ceil(num_rows/len(core_block)) + print('num_cores_y:', self.num_cores_y) self.cores_per_x_block = cores_per_x_block self.cores_per_y_block = cores_per_y_block @@ -61,6 +63,7 @@ class pattern(): self.initial_y_block = initial_y_block self.final_x_block = final_x_block self.final_y_block = final_y_block + print(self.num_cols) if not OPTS.netlist_only: self.verify_interblock_dimensions() @@ -113,11 +116,16 @@ class pattern(): self.bit_rows.append(0) if(len(self.bit_cols) <= row + dr): self.bit_cols.append(0) - if(self.bit_rows[col+dc] < self.num_cols and self.bit_cols[row+dr] < self.num_rows): + # print(self.bit_rows[col+dc], self.num_rows, self.bit_cols[row+dr], self.num_cols) + if(self.bit_rows[col+dc] < self.num_rows and self.bit_cols[row+dr] < self.num_cols): if(inst.is_bitcell): self.bit_rows[col+dc] += 1 self.bit_cols[row+dr] += 1 + print(self.bit_rows) + print(self.bit_cols) + print('-----------------------------------') self.parent_design.cell_inst[row + dr, col + dc] = self.parent_design.add_existing_inst(inst,"bit_r{}_c{}".format(row +dr, col+dc)) + print('inst:', row+dr, col+dc) self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(row+dr, col+dc)) def connect_array(self) -> None: @@ -132,8 +140,8 @@ class pattern(): col += len(self.core_block[0]) col = 0 row += len(self.core_block) - print(self.bit_rows) - print(self.bit_cols) + # print(self.bit_rows) + # print(self.bit_cols) print(self.parent_design.cell_inst) def place_inst(self, inst, offset) -> None: @@ -157,7 +165,7 @@ class pattern(): self.bit_rows.append(0) if(len(self.bit_cols) <= row + dr): self.bit_cols.append(0) - if(self.bit_rows[col+dc] < self.num_cols and self.bit_cols[row+dr] < self.num_rows): + if(self.bit_rows[col+dc] < self.num_rows and self.bit_cols[row+dr] < self.num_cols): inst = self.parent_design.cell_inst[row + dr, col +dc] if(inst.is_bitcell): self.bit_rows[col+dc] += 1 diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index a92d3653..872986a7 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -31,7 +31,7 @@ class array_test(openram_test): num_spare_rows = 0 num_spare_cols = 0 - a = factory.create(module_type="bitcell_array", cols=8 + num_spare_cols, rows=8 + num_spare_rows) + a = factory.create(module_type="bitcell_array", cols=4 + num_spare_cols, rows=2 + num_spare_rows) self.local_check(a) openram.end_openram()