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Create sized RBL WL driver in port_address

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mrg
2020-09-28 11:30:21 -07:00
parent c7d32089f3
commit 6f06bb9dd5
8 changed files with 21 additions and 18 deletions
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compiler/tests/04_wordline_driver_test.py
+1 -1
View File
@@ -25,7 +25,7 @@ class wordline_driver_test(openram_test):
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_driver")
tx = factory.create(module_type="wordline_driver", cols=8)
self.local_check(tx)
globals.end_openram()
compiler/tests/18_port_address_1rw_1r_test.py
+2 -2
View File
@@ -27,11 +27,11 @@ class port_address_1rw_1r_test(openram_test):
globals.setup_bitcell()
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16)
a = factory.create("port_address", cols=16, rows=16, port=0)
self.local_check(a)
debug.info(1, "Port address 256 rows")
a = factory.create("port_address", cols=256, rows=256)
a = factory.create("port_address", cols=256, rows=256, port=1)
self.local_check(a)
globals.end_openram()
compiler/tests/18_port_address_test.py
+2 -2
View File
@@ -21,11 +21,11 @@ class port_address_test(openram_test):
globals.init_openram(config_file)
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16)
a = factory.create("port_address", cols=16, rows=16, port=0)
self.local_check(a)
debug.info(1, "Port address 512 rows")
a = factory.create("port_address", cols=256, rows=512)
a = factory.create("port_address", cols=256, rows=512, port=0)
self.local_check(a)
globals.end_openram()