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Create sized RBL WL driver in port_address

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mrg
2020-09-28 11:30:21 -07:00
parent c7d32089f3
commit 6f06bb9dd5
8 changed files with 21 additions and 18 deletions
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compiler/pgates/wordline_driver.py
+1 -1
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@@ -18,7 +18,7 @@ class wordline_driver(design.design):
This is an AND (or NAND) with configurable drive strength to drive the wordlines.
It is matched to the bitcell height.
"""
def __init__(self, name, cols=1, height=None):
def __init__(self, name, cols, height=None):
debug.info(1, "Creating wordline_driver {}".format(name))
self.add_comment("cols: {}".format(cols))
super().__init__(name)