Create sized RBL WL driver in port_address

2026-08-30 01:48:33 +02:00 · 2020-09-28 11:30:21 -07:00
parent c7d32089f3
commit 6f06bb9dd5
8 changed files with 21 additions and 18 deletions
@@ -207,9 +207,9 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
                
                y_offset = in_pin.cy()
                if port == 0:
-                    y_offset -= 1.5 * self.m3_pitch
+                    y_offset -= 2 * self.m3_pitch
                else:
-                    y_offset += 1.5 * self.m3_pitch
+                    y_offset += 2 * self.m3_pitch
                    
                self.add_layout_pin_segment_center(text=wl_name,
                                                   layer="m3",