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Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.

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Hunter Nichols
2018-10-26 00:08:13 -07:00
parent 8e243258e4
commit 6efe0f56c2
6 changed files with 150 additions and 135 deletions
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compiler/tests/05_bitcell_1rw_1r_array_test.py
+1 -1
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@@ -19,7 +19,7 @@ class bitcell_1rw_1r_array_test(openram_test):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(2, "Testing 4x4 array for 6t_cell")
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1