From 6efe0f56c2e2dbfce72130119d597235757faa39 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 25 Oct 2018 14:53:03 -0700 Subject: [PATCH] Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. --- compiler/bitcells/bitcell_1rw_1r.py | 13 +- .../tests/05_bitcell_1rw_1r_array_test.py | 2 +- technology/freepdk45/gds_lib/cell_1rw_1r.gds | Bin 16384 -> 16384 bytes technology/scn4m_subm/gds_lib/cell_1rw_1r.gds | Bin 0 -> 6202 bytes technology/scn4m_subm/mag_lib/cell_1rw_1r.mag | 256 +++++++++--------- technology/scn4m_subm/sp_lib/cell_1rw_1r.sp | 14 + 6 files changed, 150 insertions(+), 135 deletions(-) create mode 100644 technology/scn4m_subm/gds_lib/cell_1rw_1r.gds create mode 100644 technology/scn4m_subm/sp_lib/cell_1rw_1r.sp diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index 1f5721fc..2f13a910 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -21,7 +21,6 @@ class bitcell_1rw_1r(design.design): self.width = bitcell_1rw_1r.width self.height = bitcell_1rw_1r.height - debug.info(1, "Multiport width {}, height {}".format(self.width, self.height)) self.pin_map = bitcell_1rw_1r.pin_map def analytical_delay(self, slew, load=0, swing = 0.5): @@ -39,12 +38,12 @@ class bitcell_1rw_1r(design.design): def list_bitcell_pins(self, col, row): """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ - bitcell_pins = ["bl0[{0}]".format(col), - "br0[{0}]".format(col), - "bl1[{0}]".format(col), - "br1[{0}]".format(col), - "wl0[{0}]".format(row), - "wl1[{0}]".format(row), + bitcell_pins = ["bl0_{0}".format(col), + "br0_{0}".format(col), + "bl1_{0}".format(col), + "br1_{0}".format(col), + "wl0_{0}".format(row), + "wl1_{0}".format(row), "vdd", "gnd"] return bitcell_pins diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 04afa899..68dcc409 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -19,7 +19,7 @@ class bitcell_1rw_1r_array_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import bitcell_array - debug.info(2, "Testing 4x4 array for 6t_cell") + debug.info(2, "Testing 4x4 array for cell_1rw_1r") OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds index c282b61c0cc98469cab0e4c464a52c6d7403790c..fe12fc729b64479255fb28bbf2bad3acd31eec47 100644 GIT binary patch literal 16384 zcmeHOS&SXU6|L@hulsrC&1f)@0W*LxQKUG?n$3d;vB((sz<5#Y9~!Q|YkzFk$_UA??{ zM0~uKdQQJved^x2b#E=*Jt7dksEYy57t^9!TqqU_Ph1{f`=VDY@`DWrem1>*>dv38 zT061h7k5qV+atsey6V?0IsW(yXEy$4eCh2MoLc+4Wn!SNYa!-MqA4yD{eq55gJA8@ z#D?{^Zk||uvX{!YHqxb|rdqzu*K_HpDXG8M zbL+B3$`x(%T$k17|NoJ)WzR)1+j7qrcpmvWxntknsZ_oW>3mH@E#(SM8Y>xT#-T`N zyxAIS5>bcy=pa5FK(9~n86h>tD!c78w_k&k#%sp+!6!N6HHu%*cC1eJ?%8+O#Prn8 zRPzVp$g{OiK?@FVOrx|Kaz>OmtVhX==Ft_^EJC)M(W$>BekyBaJCUu7 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22 33 +rect 24 29 25 41 +rect 29 29 30 41 +rect 32 33 33 41 +rect 37 35 38 41 +rect 40 39 45 41 +rect 40 35 41 39 +rect 32 29 37 33 +rect 9 23 14 25 +rect 13 19 14 23 +rect 9 17 14 19 +rect 16 17 22 25 +rect 24 17 25 25 +rect 29 17 30 25 +rect 32 17 38 25 +rect 40 23 45 25 +rect 40 19 41 23 +rect 40 17 45 19 << pdiffusion >> -rect 1 5 2 9 -rect 4 5 5 9 -rect 9 5 10 9 -rect 12 5 13 9 +rect 21 58 22 62 +rect 24 58 25 62 +rect 29 58 30 62 +rect 32 58 33 62 << ndcontact >> -rect -11 -18 -7 -14 -rect -3 -20 1 -12 -rect 5 -24 9 -12 -rect 13 -20 17 -12 -rect 21 -18 25 -14 -rect -11 -34 -7 -30 -rect 5 -36 9 -28 -rect 21 -34 25 -30 +rect 9 35 13 39 +rect 17 33 21 41 +rect 25 29 29 41 +rect 33 33 37 41 +rect 41 35 45 39 +rect 9 19 13 23 +rect 25 17 29 25 +rect 41 19 45 23 << pdcontact >> -rect -3 5 1 9 -rect 5 5 9 9 -rect 13 5 17 9 +rect 17 58 21 62 +rect 25 58 29 62 +rect 33 58 37 62 << psubstratepcontact >> -rect 5 -44 9 -40 +rect 25 9 29 13 << nsubstratencontact >> -rect 5 19 9 23 +rect 25 72 29 76 << polysilicon >> -rect 2 9 4 11 -rect 10 9 12 11 -rect 2 -5 4 5 -rect 10 2 12 5 -rect 11 -2 12 2 -rect -6 -12 -4 -7 -rect 2 -9 3 -5 -rect 2 -12 4 -9 -rect 10 -12 12 -2 -rect 18 -12 20 -7 -rect -6 -20 -4 -18 -rect 18 -20 20 -18 -rect -6 -28 -4 -27 -rect 2 -28 4 -24 -rect 10 -28 12 -24 -rect 18 -28 20 -27 -rect -6 -38 -4 -36 -rect 2 -38 4 -36 -rect 10 -38 12 -36 -rect 18 -38 20 -36 +rect 22 62 24 64 +rect 30 62 32 64 +rect 22 48 24 58 +rect 30 55 32 58 +rect 31 51 32 55 +rect 14 41 16 46 +rect 22 44 23 48 +rect 22 41 24 44 +rect 30 41 32 51 +rect 38 41 40 46 +rect 14 33 16 35 +rect 38 33 40 35 +rect 14 25 16 26 +rect 22 25 24 29 +rect 30 25 32 29 +rect 38 25 40 26 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 << polycontact >> -rect 7 -2 11 2 -rect -10 -11 -6 -7 -rect 3 -9 7 -5 -rect 20 -11 24 -7 -rect -8 -27 -4 -23 -rect 18 -27 22 -23 +rect 27 51 31 55 +rect 10 42 14 46 +rect 23 44 27 48 +rect 40 42 44 46 +rect 12 26 16 30 +rect 38 26 42 30 << metal1 >> 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48 35 52 39 +rect 34 26 38 30 +rect 9 19 13 23 +rect 41 19 45 23 +rect 16 2 20 6 +rect 34 2 38 6 << metal2 >> -rect -18 -14 -14 23 -rect -18 -51 -14 -18 -rect -11 -30 -7 23 -rect 5 9 9 19 -rect -11 -51 -7 -34 -rect -4 -47 0 -27 -rect 14 -47 18 -27 -rect 21 -30 25 23 -rect 21 -51 25 -34 -rect 28 -14 32 23 -rect 28 -51 32 -18 +rect 2 39 6 76 +rect 2 0 6 35 +rect 9 23 13 76 +rect 25 62 29 72 +rect 9 0 13 19 +rect 16 6 20 26 +rect 34 6 38 26 +rect 41 23 45 76 +rect 41 0 45 19 +rect 48 39 52 76 +rect 48 0 52 35 +<< bb >> +rect 0 0 54 74 << labels >> -rlabel metal1 7 -49 7 -49 1 wl1 -rlabel psubstratepcontact 7 -42 7 -42 1 gnd -rlabel m2contact 7 21 7 21 5 vdd -rlabel metal1 -1 14 -1 14 1 wl0 -rlabel metal2 -16 -46 -16 -46 2 bl0 -rlabel metal2 -9 -46 -9 -46 1 bl1 -rlabel metal2 23 -46 23 -46 1 br1 -rlabel metal2 30 -46 30 -46 8 br0 +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel m2contact 27 74 27 74 5 vdd +rlabel metal1 19 67 19 67 1 wl0 +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 << end >> diff --git a/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp new file mode 100644 index 00000000..1a52d8d0 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/cell_1rw_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd n w=1.6u l=0.4u +MM8 RA_to_R_right Q gnd gnd n w=1.6u l=0.4u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.6u l=0.4u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.6u l=0.4u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.4u +MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.4u +MM1 Q Q_bar gnd gnd n w=2.4u l=0.4u +MM0 Q_bar Q gnd gnd n w=2.4u l=0.4u +MM3 Q Q_bar vdd vdd p w=0.8u l=0.4u +MM2 Q_bar Q vdd vdd p w=0.8u l=0.4u +.ENDS +