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Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.

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Hunter Nichols
2018-10-26 00:08:13 -07:00
parent 8e243258e4
commit 6efe0f56c2
6 changed files with 150 additions and 135 deletions
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compiler/bitcells/bitcell_1rw_1r.py
+6 -7
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@@ -21,7 +21,6 @@ class bitcell_1rw_1r(design.design):
self.width = bitcell_1rw_1r.width
self.height = bitcell_1rw_1r.height
debug.info(1, "Multiport width {}, height {}".format(self.width, self.height))
self.pin_map = bitcell_1rw_1r.pin_map
def analytical_delay(self, slew, load=0, swing = 0.5):
@@ -39,12 +38,12 @@ class bitcell_1rw_1r(design.design):
def list_bitcell_pins(self, col, row):
""" Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
bitcell_pins = ["bl0[{0}]".format(col),
"br0[{0}]".format(col),
"bl1[{0}]".format(col),
"br1[{0}]".format(col),
"wl0[{0}]".format(row),
"wl1[{0}]".format(row),
bitcell_pins = ["bl0_{0}".format(col),
"br0_{0}".format(col),
"bl1_{0}".format(col),
"br1_{0}".format(col),
"wl0_{0}".format(row),
"wl1_{0}".format(row),
"vdd",
"gnd"]
return bitcell_pins
compiler/tests/05_bitcell_1rw_1r_array_test.py
+1 -1
View File
@@ -19,7 +19,7 @@ class bitcell_1rw_1r_array_test(openram_test):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(2, "Testing 4x4 array for 6t_cell")
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1