mirror of https://github.com/VLSIDA/OpenRAM.git
Blackbox option for DRC waivers
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@ -86,8 +86,6 @@ class options(optparse.Values):
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check_lvsdrc = False
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check_lvsdrc = False
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# This determines whether LVS and DRC is checked for every submodule.
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# This determines whether LVS and DRC is checked for every submodule.
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inline_lvsdrc = False
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inline_lvsdrc = False
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# Treat the bitcell as a black box (no DRC, LVS, or extraction)
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blackbox_bitcell = False
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# Remove noncritical memory cells for characterization speed-up
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# Remove noncritical memory cells for characterization speed-up
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trim_netlist = False
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trim_netlist = False
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# Run with extracted parasitics
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# Run with extracted parasitics
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@ -42,6 +42,11 @@ def setup_files():
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files = os.listdir(gds_dir)
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files = os.listdir(gds_dir)
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nametest = re.compile("\.gds$", re.IGNORECASE)
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nametest = re.compile("\.gds$", re.IGNORECASE)
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gds_files = list(filter(nametest.search, files))
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gds_files = list(filter(nametest.search, files))
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import tech
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if tech.blackbox_bitcell:
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# Ignore DRC of all bitcells
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nametest = re.compile("cell", re.IGNORECASE)
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gds_files = list(filter(lambda v: not nametest.search(v), gds_files))
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return (gds_dir, gds_files)
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return (gds_dir, gds_files)
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@ -344,6 +344,8 @@ drc_name = "calibre"
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lvs_name = "calibre"
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lvs_name = "calibre"
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pex_name = "calibre"
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pex_name = "calibre"
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blackbox_bitcell = False
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###################################################
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###################################################
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##END Technology Tool Preferences
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##END Technology Tool Preferences
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###################################################
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###################################################
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@ -310,6 +310,8 @@ drc_name = "magic"
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lvs_name = "netgen"
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lvs_name = "netgen"
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pex_name = "magic"
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pex_name = "magic"
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blackbox_bitcell = False
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###################################################
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###################################################
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##END Technology Tool Preferences
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##END Technology Tool Preferences
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###################################################
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###################################################
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