From 6e2f60353c3ccf86d6cfd1ed78961817bafbc635 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 25 Mar 2021 10:00:24 -0700 Subject: [PATCH] Add wells to driver stages. Remove unnecessary height/center in control logic. --- compiler/modules/control_logic.py | 2 -- compiler/pgates/pdriver.py | 4 +--- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 5aec6872..eb9a21ed 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -338,8 +338,6 @@ class control_logic(design.design): row += 1 if (self.port_type == "rw") or (self.port_type == "w"): self.place_wen_row(row) - height = self.w_en_gate_inst.uy() - control_center_y = self.w_en_gate_inst.uy() row += 1 self.place_pen_row(row) row += 1 diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 4662577b..bbadb9ab 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -87,13 +87,11 @@ class pdriver(pgate.pgate): def add_modules(self): self.inv_list = [] - add_well = self.add_wells for size in self.size_list: temp_inv = factory.create(module_type="pinv", size=size, height=self.height, - add_wells=add_well) - add_well=False + add_wells=self.add_wells) self.inv_list.append(temp_inv) self.add_mod(temp_inv)