From 6e070925b642691f412d5fc0fcce563edef9cd3f Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Tue, 28 Jan 2020 02:32:34 +0000
Subject: [PATCH] update magic for multiport

---
 compiler/characterizer/stimuli.py |  5 +++--
 compiler/sram/sram_base.py        | 10 ++--------
 compiler/verify/magic.py          |  1 +
 3 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py
index 198dacdd..5e0bd52e 100644
--- a/compiler/characterizer/stimuli.py
+++ b/compiler/characterizer/stimuli.py
@@ -63,8 +63,9 @@ class stimuli():
                     self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
                     self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
             for col in range(OPTS.word_size):
-                    self.sf.write("bl{0}_{2} ".format(bank, row, col))
-                    self.sf.write("br{0}_{2} ".format(bank, row, col))
+                for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
+                    self.sf.write("bl{0}_{2} ".format(port, row, col))
+                    self.sf.write("br{0}_{2} ".format(port, row, col))
                   
 
             self.sf.write("s_en{0} ".format(bank))
diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py
index 8d4bc330..bdb84b97 100644
--- a/compiler/sram/sram_base.py
+++ b/compiler/sram/sram_base.py
@@ -128,19 +128,13 @@ class sram_base(design, verilog, lef):
                 col = br_meta[cell][0][2]
                 for bitline in range(len(br_offsets[cell])):
                     bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]]
-                    br.append([bitline_location, br_meta[cell][bitline][3], col])
-
-            
-            
+                    br.append([bitline_location, br_meta[cell][bitline][3], col])           
 
             for i in range(len(bl)):
                 self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0])               
 
             for i in range(len(br)):
-                self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])                  
-
-           
-            
+                self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])                           
 
         # add pex labels for control logic
         for i in range  (len(self.control_logic_insts)):
diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py
index 93472e2a..432325ea 100644
--- a/compiler/verify/magic.py
+++ b/compiler/verify/magic.py
@@ -420,6 +420,7 @@ def correct_port(name, output_file_name, ref_file_name):
                 bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col)
                 bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col)
         for col in range(OPTS.word_size):
+            for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
                 bitcell_list += "bl{0}_{2} ".format(bank, row, col)
                 bitcell_list += "br{0}_{2} ".format(bank, row, col)
     bitcell_list += "\n"