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Consistent naming in example configs

This commit is contained in:
mrg 2020-11-18 09:59:38 -08:00
parent 305b546ad5
commit 6cfa20731c
23 changed files with 187 additions and 144 deletions
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14
compiler/example_configs/big_config_scn4m_subm.py
View File

@ -1,12 +1,22 @@
word_size = 32 word_size = 32
num_words = 128 num_words = 128
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "scn4m_subm" tech_name = "scn4m_subm"
nominal_corner_only = False nominal_corner_only = False
process_corners = ["TT"] process_corners = ["TT"]
supply_voltages = [5.0] supply_voltages = [5.0]
temperatures = [25] temperatures = [25]
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) num_r_ports,
num_w_ports,
word_size,
num_words,
tech_name)
output_path = "macro/{}".format(output_name)

7
compiler/example_configs/example_config_1rw_1r_scn4m_subm.py
View File

@ -14,7 +14,10 @@ temperatures = [25]
route_supplies = True route_supplies = True
check_lvsdrc = True check_lvsdrc = True
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

7
compiler/example_configs/example_config_1rw_1w_scn4m_subm.py
View File

@ -15,7 +15,10 @@ temperatures = [25]
route_supplies = False route_supplies = False
check_lvsdrc = True check_lvsdrc = True
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

7
compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py
View File

@ -15,7 +15,10 @@ temperatures = [25]
# route_supplies = True # route_supplies = True
check_lvsdrc = True check_lvsdrc = True
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_1rw_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

7
compiler/example_configs/example_config_1w_1r_scn4m_subm.py
View File

@ -14,8 +14,11 @@ temperatures = [25]
route_supplies = True route_supplies = True
check_lvsdrc = True check_lvsdrc = True
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

7
compiler/example_configs/example_config_2rw_scn4m_subm.py
View File

@ -14,8 +14,11 @@ temperatures = [25]
route_supplies = False route_supplies = False
check_lvsdrc = True check_lvsdrc = True
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

12
compiler/example_configs/example_config_freepdk45.py
View File

@ -1,6 +1,11 @@
word_size = 2 word_size = 2
num_words = 16 num_words = 16
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "freepdk45" tech_name = "freepdk45"
nominal_corner_only = False nominal_corner_only = False
process_corners = ["TT"] process_corners = ["TT"]
@ -13,8 +18,11 @@ check_lvsdrc = True
load_scales = [0.5, 1, 4] load_scales = [0.5, 1, 4]
slew_scales = [0.5, 1] slew_scales = [0.5, 1]
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/example_config_scn4m_subm.py
View File

@ -1,6 +1,10 @@
word_size = 2 word_size = 2
num_words = 16 num_words = 16
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "scn4m_subm" tech_name = "scn4m_subm"
nominal_corner_only = False nominal_corner_only = False
process_corners = ["TT"] process_corners = ["TT"]
@ -10,8 +14,11 @@ temperatures = [25]
route_supplies = True route_supplies = True
check_lvsdrc = True check_lvsdrc = True
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

16
compiler/example_configs/giant_config_scn4m_subm.py
View File

@ -1,13 +1,21 @@
word_size = 64 word_size = 64
num_words = 1024 num_words = 1024
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "scn4m_subm" tech_name = "scn4m_subm"
nominal_corner_only = False nominal_corner_only = False
process_corners = ["TT"] process_corners = ["TT"]
supply_voltages = [ 5.0 ] supply_voltages = [5.0]
temperatures = [ 25 ] temperatures = [25]
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/medium_config_scn4m_subm.py
View File

@ -1,14 +1,21 @@
word_size = 16 word_size = 16
num_words = 256 num_words = 256
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
tech_name = "scn4m_subm" tech_name = "scn4m_subm"
nominal_corner_only = False nominal_corner_only = False
process_corners = ["TT"] process_corners = ["TT"]
supply_voltages = [5.0] supply_voltages = [5.0]
temperatures = [25] temperatures = [25]
output_path = "temp" output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
output_name = "sram_{0}_{1}_{2}".format(word_size, num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

12
compiler/example_configs/riscv-freepdk45-8kbyte.py
View File

@ -16,11 +16,11 @@ check_lvsdrc = False
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = False
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py
View File

@ -14,11 +14,10 @@ check_lvsdrc = True
perimeter_pins = True perimeter_pins = True
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py
View File

@ -14,11 +14,10 @@ check_lvsdrc = True
perimeter_pins = True perimeter_pins = True
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-scn4m_subm-32kbyte.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = False
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py
View File

@ -14,11 +14,10 @@ check_lvsdrc = True
perimeter_pins = True perimeter_pins = True
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = False
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-sky130-1kbyte-1rw.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = True
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = True
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-sky130-2kbyte-1rw.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = True
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = True
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-sky130-4kbyte-1rw.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = True
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)

11
compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py
View File

@ -16,11 +16,10 @@ check_lvsdrc = True
perimeter_pins = False perimeter_pins = False
#netlist_only = True #netlist_only = True
#analytical_delay = False #analytical_delay = False
output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
num_r_ports,
num_w_ports,
word_size,
num_words, num_words,
write_size,
tech_name)
output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size,
num_words,
write_size,
tech_name) tech_name)
output_path = "macro/{}".format(output_name)