From 6cfa20731c09d0526adf6d348ae350931b8fd9be Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 18 Nov 2020 09:59:38 -0800 Subject: [PATCH] Consistent naming in example configs --- .../example_configs/big_config_scn4m_subm.py | 14 +++++++++++-- .../example_config_1rw_1r_scn4m_subm.py | 11 ++++++---- .../example_config_1rw_1w_scn4m_subm.py | 11 ++++++---- .../example_config_1rw_2mux_scn4m_subm.py | 11 ++++++---- .../example_config_1w_1r_scn4m_subm.py | 11 ++++++---- .../example_config_2rw_scn4m_subm.py | 11 ++++++---- .../example_config_freepdk45.py | 16 +++++++++++---- .../example_config_scn4m_subm.py | 15 ++++++++++---- .../giant_config_scn4m_subm.py | 20 +++++++++++++------ .../medium_config_scn4m_subm.py | 15 ++++++++++---- .../example_configs/riscv-freepdk45-8kbyte.py | 16 +++++++-------- .../riscv-scn4m_subm-16kbyte-1rw1r.py | 15 +++++++------- .../riscv-scn4m_subm-1kbyte-1rw1r.py | 15 +++++++------- .../riscv-scn4m_subm-2kbyte-1rw1r.py | 15 +++++++------- .../riscv-scn4m_subm-32kbyte.py | 15 +++++++------- .../riscv-scn4m_subm-4kbyte-1rw1r.py | 15 +++++++------- .../riscv-scn4m_subm-8kbyte-1rw1r.py | 15 +++++++------- .../riscv-sky130-1kbyte-1rw.py | 15 +++++++------- .../riscv-sky130-1kbyte-1rw1r.py | 15 +++++++------- .../riscv-sky130-2kbyte-1rw.py | 15 +++++++------- .../riscv-sky130-2kbyte-1rw1r.py | 15 +++++++------- .../riscv-sky130-4kbyte-1rw.py | 15 +++++++------- .../riscv-sky130-4kbyte-1rw1r.py | 15 +++++++------- 23 files changed, 187 insertions(+), 144 deletions(-) diff --git a/compiler/example_configs/big_config_scn4m_subm.py b/compiler/example_configs/big_config_scn4m_subm.py index 15d8634e..e9b05e6b 100644 --- a/compiler/example_configs/big_config_scn4m_subm.py +++ b/compiler/example_configs/big_config_scn4m_subm.py @@ -1,12 +1,22 @@ word_size = 32 num_words = 128 +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + + tech_name = "scn4m_subm" nominal_corner_only = False process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] -output_path = "temp" -output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py index 46722ac9..53371b66 100644 --- a/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py @@ -14,7 +14,10 @@ temperatures = [25] route_supplies = True check_lvsdrc = True -output_path = "temp" -output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/example_config_1rw_1w_scn4m_subm.py b/compiler/example_configs/example_config_1rw_1w_scn4m_subm.py index 360447e9..a1d6dcab 100644 --- a/compiler/example_configs/example_config_1rw_1w_scn4m_subm.py +++ b/compiler/example_configs/example_config_1rw_1w_scn4m_subm.py @@ -15,7 +15,10 @@ temperatures = [25] route_supplies = False check_lvsdrc = True -output_path = "temp" -output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py b/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py index 5f20b336..fa17dae0 100644 --- a/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py +++ b/compiler/example_configs/example_config_1rw_2mux_scn4m_subm.py @@ -15,7 +15,10 @@ temperatures = [25] # route_supplies = True check_lvsdrc = True -output_path = "temp" -output_name = "sram_1rw_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py index 9fe143a5..a7044e00 100644 --- a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py @@ -14,8 +14,11 @@ temperatures = [25] route_supplies = True check_lvsdrc = True -output_path = "temp" -output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/example_config_2rw_scn4m_subm.py b/compiler/example_configs/example_config_2rw_scn4m_subm.py index 3d0721cc..a0d92fcc 100644 --- a/compiler/example_configs/example_config_2rw_scn4m_subm.py +++ b/compiler/example_configs/example_config_2rw_scn4m_subm.py @@ -14,8 +14,11 @@ temperatures = [25] route_supplies = False check_lvsdrc = True -output_path = "temp" -output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/example_config_freepdk45.py b/compiler/example_configs/example_config_freepdk45.py index 27b4c79a..15a67f82 100644 --- a/compiler/example_configs/example_config_freepdk45.py +++ b/compiler/example_configs/example_config_freepdk45.py @@ -1,6 +1,11 @@ word_size = 2 num_words = 16 +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + + tech_name = "freepdk45" nominal_corner_only = False process_corners = ["TT"] @@ -13,8 +18,11 @@ check_lvsdrc = True load_scales = [0.5, 1, 4] slew_scales = [0.5, 1] -output_path = "temp" -output_name = "sram_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/example_config_scn4m_subm.py b/compiler/example_configs/example_config_scn4m_subm.py index 4cfe2c07..d331c1fc 100644 --- a/compiler/example_configs/example_config_scn4m_subm.py +++ b/compiler/example_configs/example_config_scn4m_subm.py @@ -1,6 +1,10 @@ word_size = 2 num_words = 16 +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + tech_name = "scn4m_subm" nominal_corner_only = False process_corners = ["TT"] @@ -10,8 +14,11 @@ temperatures = [25] route_supplies = True check_lvsdrc = True -output_path = "temp" -output_name = "sram_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/giant_config_scn4m_subm.py b/compiler/example_configs/giant_config_scn4m_subm.py index 7d683088..c9461d21 100644 --- a/compiler/example_configs/giant_config_scn4m_subm.py +++ b/compiler/example_configs/giant_config_scn4m_subm.py @@ -1,13 +1,21 @@ word_size = 64 num_words = 1024 +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + + tech_name = "scn4m_subm" nominal_corner_only = False process_corners = ["TT"] -supply_voltages = [ 5.0 ] -temperatures = [ 25 ] +supply_voltages = [5.0] +temperatures = [25] -output_path = "temp" -output_name = "sram_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/medium_config_scn4m_subm.py b/compiler/example_configs/medium_config_scn4m_subm.py index dc3ec36f..fbb49037 100644 --- a/compiler/example_configs/medium_config_scn4m_subm.py +++ b/compiler/example_configs/medium_config_scn4m_subm.py @@ -1,14 +1,21 @@ word_size = 16 num_words = 256 +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 + tech_name = "scn4m_subm" nominal_corner_only = False process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] -output_path = "temp" -output_name = "sram_{0}_{1}_{2}".format(word_size, - num_words, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-freepdk45-8kbyte.py b/compiler/example_configs/riscv-freepdk45-8kbyte.py index ad7d6072..2547c391 100644 --- a/compiler/example_configs/riscv-freepdk45-8kbyte.py +++ b/compiler/example_configs/riscv-freepdk45-8kbyte.py @@ -16,11 +16,11 @@ check_lvsdrc = False perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) + +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py b/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py index 5ca44842..5785b94f 100644 --- a/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py @@ -16,11 +16,10 @@ check_lvsdrc = False perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py b/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py index 9572aeaf..1a3e3674 100644 --- a/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py @@ -14,11 +14,10 @@ check_lvsdrc = True perimeter_pins = True #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py b/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py index 814d77e1..2ccbf621 100644 --- a/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py @@ -14,11 +14,10 @@ check_lvsdrc = True perimeter_pins = True #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-32kbyte.py b/compiler/example_configs/riscv-scn4m_subm-32kbyte.py index dc9a31b7..87ddb5eb 100644 --- a/compiler/example_configs/riscv-scn4m_subm-32kbyte.py +++ b/compiler/example_configs/riscv-scn4m_subm-32kbyte.py @@ -16,11 +16,10 @@ check_lvsdrc = False perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py b/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py index 5f374655..0c6ba216 100644 --- a/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py @@ -14,11 +14,10 @@ check_lvsdrc = True perimeter_pins = True #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py b/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py index 01dd6e7a..b15a9f01 100644 --- a/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py @@ -16,11 +16,10 @@ check_lvsdrc = False perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw.py b/compiler/example_configs/riscv-sky130-1kbyte-1rw.py index 7d68dbd1..9bdf47ed 100644 --- a/compiler/example_configs/riscv-sky130-1kbyte-1rw.py +++ b/compiler/example_configs/riscv-sky130-1kbyte-1rw.py @@ -16,11 +16,10 @@ check_lvsdrc = True perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py b/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py index f33ad55a..20463a99 100644 --- a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py @@ -16,11 +16,10 @@ check_lvsdrc = True perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw.py b/compiler/example_configs/riscv-sky130-2kbyte-1rw.py index 482eebc5..b85df3f9 100644 --- a/compiler/example_configs/riscv-sky130-2kbyte-1rw.py +++ b/compiler/example_configs/riscv-sky130-2kbyte-1rw.py @@ -16,11 +16,10 @@ check_lvsdrc = True perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py b/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py index c2a90a36..e94882e9 100644 --- a/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py @@ -16,11 +16,10 @@ check_lvsdrc = True perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw.py b/compiler/example_configs/riscv-sky130-4kbyte-1rw.py index 9e11116e..1b6cdc07 100644 --- a/compiler/example_configs/riscv-sky130-4kbyte-1rw.py +++ b/compiler/example_configs/riscv-sky130-4kbyte-1rw.py @@ -16,11 +16,10 @@ check_lvsdrc = True perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name) diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py b/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py index 2da1c708..2d53df31 100644 --- a/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py +++ b/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py @@ -16,11 +16,10 @@ check_lvsdrc = True perimeter_pins = False #netlist_only = True #analytical_delay = False -output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) -output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, - num_words, - write_size, - tech_name) +output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, + num_r_ports, + num_w_ports, + word_size, + num_words, + tech_name) +output_path = "macro/{}".format(output_name)