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OpenRAM
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Merge branch 'dev' into spmodels

This commit is contained in:
mrg 2020-10-12 15:51:40 -07:00
parent ef310970bf c3d6be27be
commit 6b56c833df
3 changed files with 7 additions and 11 deletions
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10
compiler/custom/s8_row_end.py
View File

@ -9,16 +9,14 @@
import debug import debug
import design import design
import utils import utils
from globals import OPTS from tech import layer, GDS
from tech import parameter, drc, layer, GDS
class s8_row_end(design.design): class s8_row_end(design.design):
def __init__(self, version, name=""): def __init__(self, version, name=""):
super().__init__(name) super().__init__(name)
pin_names = ["wl", "vpwr"] pin_names = ["wl", "vpwr"]
type_list = ["OUTPUT", "POWER"]
if version == "rowend": if version == "rowend":
self.name = "s8sram16x16_rowend" self.name = "s8sram16x16_rowend"
@ -29,10 +27,8 @@ class s8_row_end(design.design):
design.design.__init__(self, name=self.name) design.design.__init__(self, name=self.name)
(self.width, self.height) = utils.get_libcell_size(self.name, (self.width, self.height) = utils.get_libcell_size(self.name,
GDS["unit"], GDS["unit"],
layer["mem"], layer["mem"])
"s8sram16x16_rowend_ce\x00")
self.pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"]) self.pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
self.add_pin("wl", "OUTPUT") self.add_pin("wl", "OUTPUT")
self.add_pin("vpwr", "POWER") self.add_pin("vpwr", "POWER")

4
compiler/modules/bitcell_base_array.py
View File

@ -56,8 +56,8 @@ class bitcell_base_array(design.design):
# def get_all_wordline_names(self, prefix=""): # def get_all_wordline_names(self, prefix=""):
# return [prefix + x for x in self.all_wordline_names] # return [prefix + x for x in self.all_wordline_names]
def create_all_wordline_names(self, num_remove_wordline=0): def create_all_wordline_names(self, remove_num_wordlines=0):
for row in range(self.row_size - num_remove_wordline): for row in range(self.row_size - remove_num_wordlines):
for port in self.all_ports: for port in self.all_ports:
if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) self.wordline_names[port].append("wl_{0}_{1}".format(port, row))

2
compiler/modules/replica_column.py
View File

@ -67,7 +67,7 @@ class replica_column(bitcell_base_array):
try: try:
if cell_properties.bitcell.end_caps: if cell_properties.bitcell.end_caps:
# remove 2 wordlines to account for top/bot # remove 2 wordlines to account for top/bot
self.create_all_wordline_names(num_remove_wordlines=2) self.create_all_wordline_names(remove_num_wordlines=2)
else: else:
self.create_all_wordline_names() self.create_all_wordline_names()
except AttributeError: except AttributeError: