From 3648401e674f5e0a894f20110b6a8132f1474026 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Thu, 8 Oct 2020 16:58:19 -0700
Subject: [PATCH 1/2] Remove another boundary subcell

---
 compiler/custom/s8_row_end.py | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/compiler/custom/s8_row_end.py b/compiler/custom/s8_row_end.py
index d02ca709..e413ef40 100644
--- a/compiler/custom/s8_row_end.py
+++ b/compiler/custom/s8_row_end.py
@@ -9,16 +9,14 @@
 import debug
 import design
 import utils
-from globals import OPTS
-from tech import parameter, drc, layer, GDS
+from tech import layer, GDS
+
 
 class s8_row_end(design.design):
 
-
     def __init__(self, version, name=""):
         super().__init__(name)
         pin_names = ["wl", "vpwr"]
-        type_list = ["OUTPUT", "POWER"]
 
         if version == "rowend":
             self.name = "s8sram16x16_rowend"
@@ -28,11 +26,9 @@ class s8_row_end(design.design):
             debug.error("Invalid type for row_end", -1)
         design.design.__init__(self, name=self.name)
         (self.width, self.height) = utils.get_libcell_size(self.name,
-                                        GDS["unit"],
-                                        layer["mem"],
-                                        "s8sram16x16_rowend_ce\x00")
+                                                           GDS["unit"],
+                                                           layer["mem"])
         self.pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
 
-
         self.add_pin("wl", "OUTPUT")
         self.add_pin("vpwr", "POWER")

From c3d6be27bef0869060b548eb96cfdeb15bec2a89 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Thu, 8 Oct 2020 16:58:38 -0700
Subject: [PATCH 2/2] Fix argument name bug for remove wordlines

---
 compiler/modules/bitcell_base_array.py | 4 ++--
 compiler/modules/replica_column.py     | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py
index 71225c2c..244a9928 100644
--- a/compiler/modules/bitcell_base_array.py
+++ b/compiler/modules/bitcell_base_array.py
@@ -56,8 +56,8 @@ class bitcell_base_array(design.design):
     # def get_all_wordline_names(self, prefix=""):
     #     return [prefix + x for x in self.all_wordline_names]
 
-    def create_all_wordline_names(self, num_remove_wordline=0):
-        for row in range(self.row_size - num_remove_wordline):
+    def create_all_wordline_names(self, remove_num_wordlines=0):
+        for row in range(self.row_size - remove_num_wordlines):
             for port in self.all_ports:
                 if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
                     self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index 58939ad1..82ba1340 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -67,7 +67,7 @@ class replica_column(bitcell_base_array):
         try:
             if cell_properties.bitcell.end_caps:
                 # remove 2 wordlines to account for top/bot
-                self.create_all_wordline_names(num_remove_wordlines=2)
+                self.create_all_wordline_names(remove_num_wordlines=2)
             else:
                 self.create_all_wordline_names()
         except AttributeError: