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OpenRAM
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Fix syntax error. No DRC/LVS in netlist only mode.

This commit is contained in:
mrg 2020-04-02 11:31:28 -07:00
parent 9106e22b58
commit 67de7efd49
2 changed files with 16 additions and 4 deletions
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18
compiler/base/hierarchy_design.py
View File

@ -42,8 +42,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
def DRC_LVS(self, final_verification=False, force_check=False): def DRC_LVS(self, final_verification=False, force_check=False):
"""Checks both DRC and LVS for a module""" """Checks both DRC and LVS for a module"""
# Final verification option does not allow nets to be connected by label. # No layout to check
if OPTS.netlist_only:
return ("skipped", "skipped")
# Unit tests will check themselves. # Unit tests will check themselves.
if not force_check and OPTS.is_unit_test: if not force_check and OPTS.is_unit_test:
return ("skipped", "skipped") return ("skipped", "skipped")
@ -56,7 +58,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
self.sp_write(tempspice) self.sp_write(tempspice)
self.gds_write(tempgds) self.gds_write(tempgds)
# Final verification option does not allow nets to be connected by label.
num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) num_drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification)
num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
debug.check(num_drc_errors == 0, debug.check(num_drc_errors == 0,
@ -70,12 +72,18 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
os.remove(tempgds) os.remove(tempgds)
return (num_drc_errors, num_lvs_errors) return (num_drc_errors, num_lvs_errors)
else:
return ("skipped", "skipped")
def DRC(self, final_verification=False): def DRC(self, final_verification=False):
"""Checks DRC for a module""" """Checks DRC for a module"""
# Unit tests will check themselves. # Unit tests will check themselves.
# Do not run if disabled in options. # Do not run if disabled in options.
# No layout to check
if OPTS.netlist_only:
return "skipped"
if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
self.gds_write(tempgds) self.gds_write(tempgds)
@ -95,6 +103,10 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
# Unit tests will check themselves. # Unit tests will check themselves.
# Do not run if disabled in options. # Do not run if disabled in options.
# No layout to check
if OPTS.netlist_only:
return "skipped"
if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name)
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)

2
compiler/characterizer/lib.py
View File

@ -621,7 +621,7 @@ class lib:
)) ))
# information of checks # information of checks
(drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, top_level=True) (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, force_check=True)
datasheet.write("{0},{1},".format(drc_errors, lvs_errors)) datasheet.write("{0},{1},".format(drc_errors, lvs_errors))
# write area # write area