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https://github.com/VLSIDA/OpenRAM.git
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Fixed error where word_size was compared to num_words and added write_size to control_logic.py
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@@ -21,7 +21,7 @@ class control_logic(design.design):
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Dynamically generated Control logic for the total SRAM circuit.
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"""
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def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""):
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def __init__(self, num_rows, words_per_row, word_size, write_size, sram=None, port_type="rw", name=""):
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""" Constructor """
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name = "control_logic_" + port_type
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design.design.__init__(self, name)
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@@ -35,6 +35,7 @@ class control_logic(design.design):
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self.words_per_row = words_per_row
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self.word_size = word_size
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self.port_type = port_type
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self.write_size = write_size
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self.num_cols = word_size*words_per_row
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self.num_words = num_rows*words_per_row
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@@ -314,7 +315,11 @@ class control_logic(design.design):
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self.input_list = ["csb", "web"]
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else:
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self.input_list = ["csb"]
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if self.word_size != self.write_size:
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print(self.word_size, self.write_size)
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self.input_list = ["wmask"]
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if self.port_type == "rw":
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self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
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else:
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