Fixed port issue in bank. Changed golden data due to netlist change.

2026-08-30 01:48:33 +02:00 · 2018-11-20 11:39:14 -08:00
parent 62cbbca852
commit 67977bab3e
2 changed files with 12 additions and 12 deletions
@@ -1281,8 +1281,8 @@ class bank(design.design):
        """Get the relative capacitance of all the clk_bar connections in the bank"""
        #Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array.
        
-        #Assume single port
-        port = 0
+        #Precharges are the all the same in Mulitport, one is picked
+        port = self.read_ports[0]
        total_clk_bar_cin = self.precharge_array[port].get_en_cin()
        return total_clk_bar_cin