From 67977bab3e02fb9e07b3a079607553cf1e7b1b8b Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 20 Nov 2018 11:39:14 -0800 Subject: [PATCH] Fixed port issue in bank. Changed golden data due to netlist change. --- compiler/modules/bank.py | 4 ++-- compiler/tests/21_ngspice_delay_test.py | 20 ++++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 41eb6483..0444d0f4 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1281,8 +1281,8 @@ class bank(design.design): """Get the relative capacitance of all the clk_bar connections in the bank""" #Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array. - #Assume single port - port = 0 + #Precharges are the all the same in Mulitport, one is picked + port = self.read_ports[0] total_clk_bar_cin = self.precharge_array[port].get_en_cin() return total_clk_bar_cin diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index b0275c1c..96b1c887 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,16 +50,16 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.16119519999999998], - 'delay_lh': [0.16119519999999998], - 'leakage_power': 0.01728358, - 'min_period': 0.469, - 'read0_power': [0.5486122], - 'read1_power': [0.5276639000000001], - 'slew_hl': [0.09102138], - 'slew_lh': [0.09102138], - 'write0_power': [0.6586793], - 'write1_power': [0.5893689999999999]} + golden_data = {'delay_hl': [0.1587689], + 'delay_lh': [0.1587689], + 'leakage_power': 0.02824871, + 'min_period': 0.43, + 'read0_power': [0.5932789], + 'read1_power': [0.5733669], + 'slew_hl': [0.09096027999999999], + 'slew_lh': [0.09096027999999999], + 'write0_power': [0.7133274], + 'write1_power': [0.6390777]} elif OPTS.tech_name == "scn4m_subm": golden_data = {'delay_hl': [1.342843], 'delay_lh': [1.342843],