mirror of https://github.com/VLSIDA/OpenRAM.git
Fix functional test clk name
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parent
4c3b171b72
commit
678b2cc3fa
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@ -349,7 +349,7 @@ class functional(simulation):
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# Generate CLK signals
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# Generate CLK signals
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for port in self.all_ports:
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for port in self.all_ports:
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self.stim.gen_pulse(sig_name="{0}{1}".format(tech.spice["clk"], port),
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self.stim.gen_pulse(sig_name="{0}{1}".format("clk", port),
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v1=self.gnd_voltage,
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v1=self.gnd_voltage,
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v2=self.vdd_voltage,
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v2=self.vdd_voltage,
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offset=self.period,
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offset=self.period,
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@ -402,7 +402,7 @@ class functional(simulation):
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# For now, only testing these using first read port.
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# For now, only testing these using first read port.
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port = self.read_ports[0]
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port = self.read_ports[0]
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self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port),
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, 0).lower())
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'{}{}_{}'.format(self.dout_name, port, 0).lower())
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self.sen_name = self.get_sen_name(self.graph.all_paths)
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self.sen_name = self.get_sen_name(self.graph.all_paths)
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