From 678b2cc3fae9a44aff054ee43e25c160ae7c6414 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 4 Sep 2019 18:59:08 -0700 Subject: [PATCH] Fix functional test clk name --- compiler/characterizer/functional.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 39dd33a2..49907b4b 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -349,7 +349,7 @@ class functional(simulation): # Generate CLK signals for port in self.all_ports: - self.stim.gen_pulse(sig_name="{0}{1}".format(tech.spice["clk"], port), + self.stim.gen_pulse(sig_name="{0}{1}".format("clk", port), v1=self.gnd_voltage, v2=self.vdd_voltage, offset=self.period, @@ -402,7 +402,7 @@ class functional(simulation): # For now, only testing these using first read port. port = self.read_ports[0] - self.graph.get_all_paths('{}{}'.format(tech.spice["clk"], port), + self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, 0).lower()) self.sen_name = self.get_sen_name(self.graph.all_paths)