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Only run DRC and LVS at SRAM level if not a unit test to reduce run time.

This commit is contained in:
mrg 2020-12-15 10:46:55 -08:00
parent 5c4389efa4
commit 6714e9fac0
1 changed files with 3 additions and 2 deletions
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5
compiler/sram/sram_base.py
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@ -207,9 +207,10 @@ class sram_base(design, verilog, lef):
ur=vector(self.width, self.height)) ur=vector(self.width, self.height))
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
# We only enable final verification if we have routed the design
self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
# We only enable final verification if we have routed the design
# Only run this if not a unit test, because unit test will also verify it.
self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
print_time("Verification", datetime.datetime.now(), start_time) print_time("Verification", datetime.datetime.now(), start_time)
def create_modules(self): def create_modules(self):