From 6714e9fac0355b8a55fc6d93bbc49d39e0cbdcdd Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 15 Dec 2020 10:46:55 -0800 Subject: [PATCH] Only run DRC and LVS at SRAM level if not a unit test to reduce run time. --- compiler/sram/sram_base.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 455d2b94..9fbdec64 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -207,9 +207,10 @@ class sram_base(design, verilog, lef): ur=vector(self.width, self.height)) start_time = datetime.datetime.now() - # We only enable final verification if we have routed the design - self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc) if not OPTS.is_unit_test: + # We only enable final verification if we have routed the design + # Only run this if not a unit test, because unit test will also verify it. + self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc) print_time("Verification", datetime.datetime.now(), start_time) def create_modules(self):