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OpenRAM
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Only unblock source/target instead of all components for cleaner routes

This commit is contained in:
mrg 2021-01-06 15:14:56 -08:00
parent 7eb1e2f2d1
commit 66ff1fe990
3 changed files with 8 additions and 7 deletions
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2
compiler/router/grid.py
View File

@ -90,6 +90,7 @@ class grid:
else: else:
self.add_map(n) self.add_map(n)
self.map[n].source=True self.map[n].source=True
self.map[n].blocked=False
self.source.add(n) self.source.add(n)
def clear_target(self): def clear_target(self):
@ -104,6 +105,7 @@ class grid:
else: else:
self.add_map(n) self.add_map(n)
self.map[n].target=True self.map[n].target=True
self.map[n].blocked=False
self.target.add(n) self.target.add(n)
def add_source(self, track_list): def add_source(self, track_list):

7
compiler/router/router.py
View File

@ -355,7 +355,7 @@ class router(router_tech):
# Start fresh. Not the best for run-time, but simpler. # Start fresh. Not the best for run-time, but simpler.
self.clear_blockages() self.clear_blockages()
# This adds the initial blockges of the design # This adds the initial blockges of the design
#print("BLOCKING:", self.blocked_grids) # print("BLOCKING:", self.blocked_grids)
self.set_blockages(self.blocked_grids, True) self.set_blockages(self.blocked_grids, True)
# Block all of the supply rails # Block all of the supply rails
@ -382,8 +382,9 @@ class router(router_tech):
# Don't mark the other components as targets since we want to route # Don't mark the other components as targets since we want to route
# directly to a rail, but unblock all the source components so we can # directly to a rail, but unblock all the source components so we can
# route over them # route over them
blockage_grids = {y for x in self.pin_groups[pin_name] for y in x.grids} # 1/6/21: This would cause things that looked like loops in the supply tree router
self.set_blockages(blockage_grids, False) # blockage_grids = {y for x in self.pin_groups[pin_name] for y in x.grids}
# self.set_blockages(blockage_grids, False)
def convert_shape_to_units(self, shape): def convert_shape_to_units(self, shape):
""" """

2
compiler/router/supply_tree_router.py
View File

@ -151,8 +151,6 @@ class supply_tree_router(router):
self.write_debug_gds("debug_route.gds", True) self.write_debug_gds("debug_route.gds", True)
def add_io_pin(self, instance, pin_name, new_name=""): def add_io_pin(self, instance, pin_name, new_name=""):
""" """
Add a signle input or output pin up to metal 3. Add a signle input or output pin up to metal 3.