mirror of https://github.com/VLSIDA/OpenRAM.git
Col decoders are anything not bitcell pitch.
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@ -78,10 +78,12 @@ class hierarchical_decoder(design.design):
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def add_decoders(self):
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def add_decoders(self):
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""" Create the decoders based on the number of pre-decodes """
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""" Create the decoders based on the number of pre-decodes """
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self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4")
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self.pre2_4 = factory.create(module_type="hierarchical_predecode2x4",
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height=self.cell_height)
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self.add_mod(self.pre2_4)
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self.add_mod(self.pre2_4)
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self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8")
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self.pre3_8 = factory.create(module_type="hierarchical_predecode3x8",
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height=self.cell_height)
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self.add_mod(self.pre3_8)
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self.add_mod(self.pre3_8)
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def determine_predecodes(self, num_inputs):
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def determine_predecodes(self, num_inputs):
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@ -24,12 +24,11 @@ class hierarchical_predecode(design.design):
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if not height:
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if not height:
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self.cell_height = b.height
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self.cell_height = b.height
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self.column_decoder = False
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self.column_decoder = False
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elif height != b.height:
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self.cell_height = height
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self.column_decoder = True
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else:
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else:
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self.cell_height = b.height
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self.cell_height = height
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self.column_decoder = False
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# If we are pitch matched to the bitcell, it's a predecoder
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# otherwise it's a column decoder (out of pgates)
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self.column_decoder = (height != b.height)
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self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
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self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
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design.design.__init__(self, name)
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design.design.__init__(self, name)
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@ -311,7 +310,7 @@ class hierarchical_predecode(design.design):
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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# In sky130, we use hand-made decoder cells with vertical power
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# In sky130, we use hand-made decoder cells with vertical power
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if not self.column_decoder:
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if OPTS.tech_name == "sky130" and not self.column_decoder:
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for n in ["vdd", "gnd"]:
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for n in ["vdd", "gnd"]:
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# This makes a wire from top to bottom for both inv and and gates
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# This makes a wire from top to bottom for both inv and and gates
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for i in [self.inv_inst, self.and_inst]:
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for i in [self.inv_inst, self.and_inst]:
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