diff --git a/compiler/characterizer/fake_sram_v2.py b/compiler/characterizer/fake_sram_v2.py
new file mode 100644
index 00000000..134c15ac
--- /dev/null
+++ b/compiler/characterizer/fake_sram_v2.py
@@ -0,0 +1,51 @@
+# This is a temp file. Remove either this or the fake_sram.py
+
+from modules import sram
+import debug
+from globals import OPTS
+import os
+
+
+class fake_sram_v2(sram):
+
+    def create_netlist(self):
+        # Make sure spice file is here
+        debug.check(os.path.exists(self.sp_name), "Spice netlist in {} not found".format(self.sp_name))
+
+    def generate_pins(self):
+        self.pins = ['vdd', 'gnd']
+        self.pins.extend(['clk{}'.format(port) for port in range(
+            OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports)])
+        for port in range(OPTS.num_rw_ports):
+            self.pins.extend(['din{0}[{1}]'.format(port, bit)
+                              for bit in range(self.num_cols)])
+            self.pins.extend(['dout{0}[{1}]'.format(port, bit)
+                              for bit in range(self.num_cols)])
+            self.pins.extend(['addr{0}[{1}]'.format(port, bit)
+                              for bit in range(self.addr_size)])
+            #if self.num_wmasks != 0:
+            #    self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
+            #                      for bit in range(self.num_wmasks)])
+
+            self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
+
+        start_port = OPTS.num_rw_ports
+        for port in range(start_port, start_port + OPTS.num_r_ports):
+            self.pins.extend(['dout{0}[{1}]'.format(port, bit)
+                              for bit in range(self.num_cols)])
+            self.pins.extend(['addr{0}[{1}]'.format(port, bit)
+                              for bit in range(self.addr_size)])
+
+            self.pins.extend(['csb{}'.format(port)])
+
+        start_port += OPTS.num_r_ports
+        for port in range(start_port, start_port + OPTS.num_w_ports):
+            self.pins.extend(['din{0}[{1}]'.format(port, bit)
+                              for bit in range(self.num_cols)])
+            self.pins.extend(['addr{0}[{1}]'.format(port, bit)
+                              for bit in range(self.addr_size)])
+            if self.num_wmasks != 0:
+                self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
+                                  for bit in range(self.num_wmasks)])
+
+            self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
diff --git a/compiler/memchar.py b/compiler/memchar.py
index 425a8abd..1d140050 100755
--- a/compiler/memchar.py
+++ b/compiler/memchar.py
@@ -39,19 +39,22 @@ init_openram(config_file=args[0], is_unit_test=False)
 print_banner()
 
 # Configure the SRAM organization (duplicated from openram.py)
-from characterizer.fake_sram import fake_sram
-s = fake_sram(name=OPTS.output_name,
-                word_size=OPTS.word_size,
-                num_words=OPTS.num_words,
-                write_size=OPTS.write_size,
-                num_banks=OPTS.num_banks,
-                words_per_row=OPTS.words_per_row,
-                num_spare_rows=OPTS.num_spare_rows,
-                num_spare_cols=OPTS.num_spare_cols)
+#from characterizer.fake_sram import fake_sram
+from modules import sram_config
+from characterizer.fake_sram_v2 import fake_sram_v2
+config = sram_config(word_size=OPTS.word_size,
+                     num_words=OPTS.num_words,
+                     write_size=OPTS.write_size,
+                     num_banks=OPTS.num_banks,
+                     words_per_row=OPTS.words_per_row,
+                     num_spare_rows=OPTS.num_spare_rows,
+                     num_spare_cols=OPTS.num_spare_cols)
+s = fake_sram_v2(name=OPTS.output_name,
+                 sram_config=config)
 
-s.parse_html(args[1])
+#s.parse_html(args[1])
 s.generate_pins()
-s.setup_multiport_constants()
+#s.setup_multiport_constants()
 
 OPTS.netlist_only = True
 OPTS.check_lvsdrc = False
diff --git a/compiler/modules/sram.py b/compiler/modules/sram.py
index 37590887..912e82c5 100644
--- a/compiler/modules/sram.py
+++ b/compiler/modules/sram.py
@@ -48,11 +48,9 @@ class sram():
                                                                                        self.num_banks))
         start_time = datetime.datetime.now()
 
-        self.name = name
-
         from .sram_1bank import sram_1bank as sram
 
-        self.s = sram(name, sram_config)
+        self.s = sram(self.name, self.config)
 
         self.s.create_netlist()
         if not OPTS.netlist_only: