luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters

Browse Source
This commit is contained in:
Michael Timothy Grimes
2018-03-08 16:39:26 -08:00
parent 0ea5d0b6a7
commit 65735c08e2
3 changed files with 51 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_array.py
+16 -8
View File
@@ -88,18 +88,26 @@ class bitcell_array(design.design):
dir_key = ""
if(OPTS.bitcell == "pbitcell"):
bitcell_nets = []
for k in range(self.num_write):
bitcell_nets.append("wbl{0}[{1}]".format(k,col))
bitcell_nets.append("wbl_bar{0}[{1}]".format(k,col))
for k in range(self.num_read):
bitcell_nets.append("rbl{0}[{1}]".format(k,col))
bitcell_nets.append("rbl_bar{0}[{1}]".format(k,col))
for k in range(self.num_write):
bitcell_nets.append("wrow{0}[{1}]".format(k,row))
for k in range(self.num_read):
bitcell_nets.append("rrow{0}[{1}]".format(k,row))
bitcell_nets.append("vdd")
bitcell_nets.append("gnd")
self.cell_inst[row,col]=self.add_inst(name=name,
mod=self.cell,
offset=[xoffset, tempy],
mirror=dir_key)
self.connect_inst(["wbl0[{0}]".format(col),
"wbl_bar0[{0}]".format(col),
"rbl0[{0}]".format(col),
"rbl_bar0[{0}]".format(col),
"wrow0[{0}]".format(row),
"rrow0[{0}]".format(row),
"vdd",
"gnd"])
self.connect_inst(bitcell_nets)
else:
self.cell_inst[row,col]=self.add_inst(name=name,
mod=self.cell,