From 64bf93e4e584fc4590eb63e23198961ee3cc6546 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 12 Feb 2020 13:19:41 +0100 Subject: [PATCH] bank: Connect instances by their individual bl/br names each module should be able to state how their bl/br lines are named. Here we always connect port_data with the bitcell_array, so port_data needs function that return the names of bl/br. Signed-off-by: Bastian Koppelmann --- compiler/modules/bank.py | 10 +++++++--- compiler/modules/port_data.py | 14 ++++++++++++++ compiler/pgates/precharge.py | 6 ++++++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 133a66c2..f5f3feb6 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -679,9 +679,13 @@ class bank(design.design): inst1 = self.bitcell_array_inst inst1_bl_name = self.bl_names[port]+"_{}" inst1_br_name = self.br_names[port]+"_{}" + + inst2_bl_name = inst2.mod.get_bl_names()+"_{}" + inst2_br_name = inst2.mod.get_br_names()+"_{}" self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) + inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, + inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name) # Connect the replica bitlines rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) @@ -786,8 +790,8 @@ class bank(design.design): def connect_bitlines(self, inst1, inst2, num_bits, - inst1_bl_name="bl_{}", inst1_br_name="br_{}", - inst2_bl_name="bl_{}", inst2_br_name="br_{}"): + inst1_bl_name, inst1_br_name, + inst2_bl_name, inst2_br_name): """ Connect the bl and br of two modules. """ diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 9e7f4048..0355fd3c 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -38,6 +38,15 @@ class port_data(design.design): self.create_layout() self.add_boundary() + def get_bl_names(self): + # bl lines are connect from the precharger + return self.precharge.get_bl_names() + + def get_br_names(self): + # br lines are connect from the precharger + return self.precharge.get_br_names() + + def create_netlist(self): self.precompute_constants() @@ -221,6 +230,11 @@ class port_data(design.design): self.bl_names = self.bitcell.get_all_bl_names() self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() + # used for bl/br names + self.precharge = factory.create(module_type="precharge", + bitcell_bl = self.bl_names[0], + bitcell_br = self.br_names[0]) + def create_precharge_array(self): """ Creating Precharge """ diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 28b4d85a..acb2062f 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -38,6 +38,12 @@ class precharge(design.design): self.create_layout() self.DRC_LVS() + def get_bl_names(self): + return "bl" + + def get_br_names(self): + return "br" + def create_netlist(self): self.add_pins() self.add_ptx()