luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 19:28:08 +02:00
Code Issues Packages Projects Releases Wiki Activity

Convert unit test 25 to new modules convert

Browse Source
This commit is contained in:
Bugra Onal
2022-08-10 16:33:50 -07:00
parent dc1626879e
commit 623c1ac02f
2 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/tests/25_verilog_multibank_test.py
+3 -3
View File
@@ -23,8 +23,8 @@ class multibank_verilog_test(openram_test):
OPTS.route_supplies=False
OPTS.check_lvsdrc=False
OPTS.netlist_only=True
from sram import sram
from sram_config import sram_config
from modules import sram
from modules import sram_config
c = sram_config(word_size=2,
num_words=16,
num_banks=2)
@@ -47,7 +47,7 @@ class multibank_verilog_test(openram_test):
multi_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile)
self.assertTrue(self.isdiff(vname, multi_golden))
one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bname)
one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bfile)
self.assertTrue(self.isdiff(v1bname, one_golden))
globals.end_openram()
compiler/tests/golden/sram_2_16_2_scn4m_subm.v
+1 -1
View File
@@ -16,7 +16,7 @@ module sram (
parameter ADDR_WIDTH= 4;
parameter BANK_SEL = 1;
parameter NUM_WMASK = 1;
parameter NUM_WMASK = 0;
`ifdef USE_POWER_PINS
inout vdd;