From 623c1ac02facd8b0ff795f93af93524be6d037af Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Wed, 10 Aug 2022 16:33:50 -0700 Subject: [PATCH] Convert unit test 25 to new modules convert --- compiler/tests/25_verilog_multibank_test.py | 6 +++--- compiler/tests/golden/sram_2_16_2_scn4m_subm.v | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/tests/25_verilog_multibank_test.py b/compiler/tests/25_verilog_multibank_test.py index ef671f2a..72449868 100755 --- a/compiler/tests/25_verilog_multibank_test.py +++ b/compiler/tests/25_verilog_multibank_test.py @@ -23,8 +23,8 @@ class multibank_verilog_test(openram_test): OPTS.route_supplies=False OPTS.check_lvsdrc=False OPTS.netlist_only=True - from sram import sram - from sram_config import sram_config + from modules import sram + from modules import sram_config c = sram_config(word_size=2, num_words=16, num_banks=2) @@ -47,7 +47,7 @@ class multibank_verilog_test(openram_test): multi_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile) self.assertTrue(self.isdiff(vname, multi_golden)) - one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bname) + one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bfile) self.assertTrue(self.isdiff(v1bname, one_golden)) globals.end_openram() diff --git a/compiler/tests/golden/sram_2_16_2_scn4m_subm.v b/compiler/tests/golden/sram_2_16_2_scn4m_subm.v index 92c18777..fe23faaf 100644 --- a/compiler/tests/golden/sram_2_16_2_scn4m_subm.v +++ b/compiler/tests/golden/sram_2_16_2_scn4m_subm.v @@ -16,7 +16,7 @@ module sram ( parameter ADDR_WIDTH= 4; parameter BANK_SEL = 1; - parameter NUM_WMASK = 1; + parameter NUM_WMASK = 0; `ifdef USE_POWER_PINS inout vdd;