diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 094d2e15..1cc2693d 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -451,15 +451,17 @@ class delay():
                 LH_slew.append(bank_delay.slew/1e3)
                 HL_slew.append(bank_delay.slew/1e3)
         
+        power = sram.analytical_power(slew, load)
+        
         data = {"min_period": 0, 
                 "delay1": LH_delay,
                 "delay0": HL_delay,
                 "slew1": LH_slew,
                 "slew0": HL_slew,
-                "read0_power": 0,
-                "read1_power": 0,
-                "write0_power": 0,
-                "write1_power": 0
+                "read0_power": power,
+                "read1_power": power,
+                "write0_power": power,
+                "write1_power": power
                 }
         return data
 
diff --git a/compiler/sram.py b/compiler/sram.py
index 9d602097..d9eb9db8 100644
--- a/compiler/sram.py
+++ b/compiler/sram.py
@@ -1003,3 +1003,7 @@ class sram(design.design):
     def analytical_delay(self,slew,load):
         """ LH and HL are the same in analytical model. """
         return self.bank.analytical_delay(slew,load)
+    
+    def analytical_power(self,slew,load):
+        """ Just a test function for the power."""
+        return 1