luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix various typos and errors

This commit is contained in:
mrg 2020-11-13 16:04:07 -08:00
parent 8021430122
commit 620e271562
4 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
compiler/bitcells/dummy_bitcell_2port.py
View File

@ -18,7 +18,7 @@ class dummy_bitcell_2port(bitcell_base.bitcell_base):
the technology library. """ the technology library. """
def __init__(self, name): def __init__(self, name):
super().__init__(name, props.bitcel_2port) super().__init__(name, props.bitcell_2port)
debug.info(2, "Create dummy bitcell 2 port object") debug.info(2, "Create dummy bitcell 2 port object")

1
compiler/bitcells/pbitcell.py
View File

@ -31,6 +31,7 @@ class pbitcell(bitcell_base.bitcell_base):
self.replica_bitcell = replica_bitcell self.replica_bitcell = replica_bitcell
self.dummy_bitcell = dummy_bitcell self.dummy_bitcell = dummy_bitcell
self.mirror = props.bitcell_1port.mirror self.mirror = props.bitcell_1port.mirror
self.end_caps = props.bitcell_1port.end_caps
bitcell_base.bitcell_base.__init__(self, name) bitcell_base.bitcell_base.__init__(self, name)
fmt_str = "{0} rw ports, {1} w ports and {2} r ports" fmt_str = "{0} rw ports, {1} w ports and {2} r ports"

5
compiler/modules/column_mux_array.py
View File

@ -11,7 +11,6 @@ from tech import layer, preferred_directions
from vector import vector from vector import vector
from sram_factory import factory from sram_factory import factory
from globals import OPTS from globals import OPTS
from tech import cell_properties as cell_props
from tech import layer_properties as layer_props from tech import layer_properties as layer_props
@ -99,6 +98,8 @@ class column_mux_array(design.design):
bitcell_br=self.bitcell_br) bitcell_br=self.bitcell_br)
self.add_mod(self.mux) self.add_mod(self.mux)
self.cell = factory.create(module_type=OPTS.bitcell)
def setup_layout_constants(self): def setup_layout_constants(self):
self.column_addr_size = int(self.words_per_row / 2) self.column_addr_size = int(self.words_per_row / 2)
self.width = self.columns * self.mux.width self.width = self.columns * self.mux.width
@ -128,7 +129,7 @@ class column_mux_array(design.design):
# For every column, add a pass gate # For every column, add a pass gate
for col_num, xoffset in enumerate(self.offsets[0:self.columns]): for col_num, xoffset in enumerate(self.offsets[0:self.columns]):
if cell_props.bitcell.mirror.y and (col_num + self.column_offset) % 2: if self.cell.mirror.y and (col_num + self.column_offset) % 2:
mirror = "MY" mirror = "MY"
xoffset = xoffset + self.mux.width xoffset = xoffset + self.mux.width
else: else:

4
compiler/modules/replica_column.py
View File

@ -126,13 +126,13 @@ class replica_column(bitcell_base_array):
# column that needs to be flipped. # column that needs to be flipped.
dir_y = False dir_y = False
xoffset = 0 xoffset = 0
if self.replica_cell.mirror.y and self.column_offset % 2: if self.cell.mirror.y and self.column_offset % 2:
dir_y = True dir_y = True
xoffset = self.replica_cell.width xoffset = self.replica_cell.width
for row in range(self.total_size): for row in range(self.total_size):
# name = "bit_r{0}_{1}".format(row, "rbl") # name = "bit_r{0}_{1}".format(row, "rbl")
dir_x = self.replica_cell.mirror.x and (row + rbl_offset) % 2 dir_x = self.cell.mirror.x and (row + rbl_offset) % 2
offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2)) offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))