diff --git a/compiler/bitcells/dummy_bitcell_2port.py b/compiler/bitcells/dummy_bitcell_2port.py
index 4d6d5c49..14b0ce96 100644
--- a/compiler/bitcells/dummy_bitcell_2port.py
+++ b/compiler/bitcells/dummy_bitcell_2port.py
@@ -18,7 +18,7 @@ class dummy_bitcell_2port(bitcell_base.bitcell_base):
     the technology library. """
 
     def __init__(self, name):
-        super().__init__(name, props.bitcel_2port)
+        super().__init__(name, props.bitcell_2port)
         debug.info(2, "Create dummy bitcell 2 port object")
 
 
diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py
index 61360e99..c5ac8cb6 100644
--- a/compiler/bitcells/pbitcell.py
+++ b/compiler/bitcells/pbitcell.py
@@ -31,6 +31,7 @@ class pbitcell(bitcell_base.bitcell_base):
         self.replica_bitcell = replica_bitcell
         self.dummy_bitcell = dummy_bitcell
         self.mirror = props.bitcell_1port.mirror
+        self.end_caps = props.bitcell_1port.end_caps
 
         bitcell_base.bitcell_base.__init__(self, name)
         fmt_str = "{0} rw ports, {1} w ports and {2} r ports"
diff --git a/compiler/modules/column_mux_array.py b/compiler/modules/column_mux_array.py
index 2f1ee56e..55d67eee 100644
--- a/compiler/modules/column_mux_array.py
+++ b/compiler/modules/column_mux_array.py
@@ -11,7 +11,6 @@ from tech import layer, preferred_directions
 from vector import vector
 from sram_factory import factory
 from globals import OPTS
-from tech import cell_properties as cell_props
 from tech import layer_properties as layer_props
 
 
@@ -99,6 +98,8 @@ class column_mux_array(design.design):
                                   bitcell_br=self.bitcell_br)
         self.add_mod(self.mux)
 
+        self.cell = factory.create(module_type=OPTS.bitcell)
+
     def setup_layout_constants(self):
         self.column_addr_size = int(self.words_per_row / 2)
         self.width = self.columns * self.mux.width
@@ -128,7 +129,7 @@ class column_mux_array(design.design):
 
         # For every column, add a pass gate
         for col_num, xoffset in enumerate(self.offsets[0:self.columns]):
-            if cell_props.bitcell.mirror.y and (col_num + self.column_offset) % 2:
+            if self.cell.mirror.y and (col_num + self.column_offset) % 2:
                 mirror = "MY"
                 xoffset = xoffset + self.mux.width
             else:
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index 1fbe60fb..eac98054 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -126,13 +126,13 @@ class replica_column(bitcell_base_array):
         # column that needs to be flipped.
         dir_y = False
         xoffset = 0
-        if self.replica_cell.mirror.y and self.column_offset % 2:
+        if self.cell.mirror.y and self.column_offset % 2:
             dir_y = True
             xoffset = self.replica_cell.width
 
         for row in range(self.total_size):
             # name = "bit_r{0}_{1}".format(row, "rbl")
-            dir_x = self.replica_cell.mirror.x and (row + rbl_offset) % 2
+            dir_x = self.cell.mirror.x and (row + rbl_offset) % 2
 
             offset = vector(xoffset, self.cell.height * (row + (row + rbl_offset) % 2))