diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6c8138fd..96e30d2d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -1,6 +1,6 @@ freepdk45: script: "/home/gitlab-runner/regress_freepdk45.sh" -scn3me_subm: - script: "/home/gitlab-runner/regress_scn3me_subm.sh" +scn4m_subm: + script: "/home/gitlab-runner/regress_scn4m_subm.sh" diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 3ac5ea63..554d6d36 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -602,6 +602,7 @@ class layout(lef.lef): """ Connect a mapping of pin -> name for a bus. This could be replaced with a channel router in the future. + NOTE: This has only really been tested with point-to-point connections (not multiple pins on a net). """ (horizontal_layer, via_layer, vertical_layer)=layer_stack if horizontal: @@ -711,16 +712,18 @@ class layout(lef.lef): self.add_wire(layer_stack, [pin.center(), mid, trunk_mid]) - def create_channel_route(self, route_map, top_pins, bottom_pins, offset, + def create_channel_route(self, netlist, pins, offset, layer_stack=("metal1", "via1", "metal2"), pitch=None, vertical=False): """ - This is a simple channel route for one-to-one connections that - will jog the top route whenever there is a conflict. It does NOT - try to minimize the number of tracks -- instead, it picks an order to avoid the vertical - conflicts between pins. - """ + The net list is a list of the nets. Each net is a list of pin + names to be connected. Pins is a dictionary of the pin names + to the pin structures. Offset is the lower-left of where the + routing channel will start. This does NOT try to minimize the + number of tracks -- instead, it picks an order to avoid the + vertical conflicts between pins. + """ def remove_net_from_graph(pin, g): # Remove the pin from the keys g.pop(pin,None) @@ -732,11 +735,32 @@ class layout(lef.lef): g[other_pin]=conflicts return g + def vcg_pins_overlap(pins1, pins2, vertical): + # Check all the pin pairs on two nets and return a pin + # overlap if any pin overlaps vertically + for pin1 in pins1: + for pin2 in pins2: + if vcg_pin_overlap(pin1, pin2, vertical): + return True + + return False + + def vcg_pin_overlap(pin1, pin2, vertical): + # Check for vertical overlap of the two pins + + # Pin 1 must be in the "TOP" set + x_overlap = pin1.by() > pin2.by() and abs(pin1.center().x-pin2.center().x)self.word_size or self.probe_data<0: debug.error("Given probe_data is not an integer to specify a data bit",1) + + #Adding port options here which the characterizer cannot handle. Some may be added later like ROM + if len(self.read_ports) == 0: + debug.error("Characterizer does not currently support SRAMs without read ports.",1) + if len(self.write_ports) == 0: + debug.error("Characterizer does not currently support SRAMs without write ports.",1) def write_generic_stimulus(self): """ Create the instance, supplies, loads, and access transistors. """ @@ -74,11 +80,13 @@ class delay(): self.sf.write("\n* Instantiation of the SRAM\n") self.stim.inst_sram(abits=self.addr_size, dbits=self.word_size, + port_info=(self.total_port_num,self.readwrite_port_num,self.read_ports,self.write_ports), sram_name=self.name) self.sf.write("\n* SRAM output loads\n") - for i in range(self.word_size): - self.sf.write("CD{0} DOUT[{0}] 0 {1}f\n".format(i,self.load)) + for port in self.read_ports: + for i in range(self.word_size): + self.sf.write("CD{0}{1} DOUT{0}[{1}] 0 {2}f\n".format(port,i,self.load)) def write_delay_stimulus(self): @@ -137,7 +145,7 @@ class delay(): self.check_arguments() # obtains list of time-points for each rising clk edge - self.create_test_cycles() + #self.create_test_cycles() # creates and opens stimulus file for writing temp_stim = "{0}/stim.sp".format(OPTS.openram_temp) @@ -155,17 +163,21 @@ class delay(): # generate data and addr signals self.sf.write("\n* Generation of data and address signals\n") - for i in range(self.word_size): - self.stim.gen_constant(sig_name="DIN[{0}]".format(i), - v_val=0) - for i in range(self.addr_size): - self.stim.gen_constant(sig_name="A[{0}]".format(i), - v_val=0) + for write_port in self.write_ports: + for i in range(self.word_size): + self.stim.gen_constant(sig_name="DIN{0}[{1}] ".format(write_port, i), + v_val=0) + for port in range(self.total_port_num): + for i in range(self.addr_size): + self.stim.gen_constant(sig_name="A{0}[{1}]".format(port, i), + v_val=0) # generate control signals self.sf.write("\n* Generation of control signals\n") - self.stim.gen_constant(sig_name="CSb", v_val=self.vdd_voltage) - self.stim.gen_constant(sig_name="WEb", v_val=self.vdd_voltage) + for port in range(self.total_port_num): + self.stim.gen_constant(sig_name="CSB{0}".format(port), v_val=self.vdd_voltage) + if port in self.read_ports and port in self.write_ports: + self.stim.gen_constant(sig_name="WEB{0}".format(port), v_val=self.vdd_voltage) self.sf.write("\n* Generation of global clock signal\n") self.stim.gen_constant(sig_name="CLK", v_val=0) @@ -177,90 +189,105 @@ class delay(): self.sf.close() - def write_delay_measures(self): + def write_delay_measures_read_port(self, port): """ - Write the measure statements to quantify the delay and power results. + Write the measure statements to quantify the delay and power results for a read port. """ - self.sf.write("\n* Measure statements for delay and power\n") - - # Output some comments to aid where cycles start and - # what is happening - for comment in self.cycle_comments: - self.sf.write("* {}\n".format(comment)) - # Trigger on the clk of the appropriate cycle trig_name = "clk" - targ_name = "{0}".format("DOUT[{0}]".format(self.probe_data)) + #Target name should be an input to the function or a member variable. That way, the ports can be singled out for testing + targ_name = "{0}".format("DOUT{0}[{1}]".format(port,self.probe_data)) trig_val = targ_val = 0.5 * self.vdd_voltage # Delay the target to measure after the negative edge - self.stim.gen_meas_delay(meas_name="DELAY_HL", + self.stim.gen_meas_delay(meas_name="DELAY_HL{0}".format(port), trig_name=trig_name, targ_name=targ_name, trig_val=trig_val, targ_val=targ_val, trig_dir="RISE", targ_dir="FALL", - trig_td=self.cycle_times[self.read0_cycle], - targ_td=self.cycle_times[self.read0_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]) - self.stim.gen_meas_delay(meas_name="DELAY_LH", + self.stim.gen_meas_delay(meas_name="DELAY_LH{0}".format(port), trig_name=trig_name, targ_name=targ_name, trig_val=trig_val, targ_val=targ_val, trig_dir="RISE", targ_dir="RISE", - trig_td=self.cycle_times[self.read1_cycle], - targ_td=self.cycle_times[self.read1_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]) - self.stim.gen_meas_delay(meas_name="SLEW_HL", + self.stim.gen_meas_delay(meas_name="SLEW_HL{0}".format(port), trig_name=targ_name, targ_name=targ_name, trig_val=0.9*self.vdd_voltage, targ_val=0.1*self.vdd_voltage, trig_dir="FALL", targ_dir="FALL", - trig_td=self.cycle_times[self.read0_cycle], - targ_td=self.cycle_times[self.read0_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]) - self.stim.gen_meas_delay(meas_name="SLEW_LH", + self.stim.gen_meas_delay(meas_name="SLEW_LH{0}".format(port), trig_name=targ_name, targ_name=targ_name, trig_val=0.1*self.vdd_voltage, targ_val=0.9*self.vdd_voltage, trig_dir="RISE", targ_dir="RISE", - trig_td=self.cycle_times[self.read1_cycle], - targ_td=self.cycle_times[self.read1_cycle]) + trig_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]], + targ_td=self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]) # add measure statements for power - t_initial = self.cycle_times[self.write0_cycle] - t_final = self.cycle_times[self.write0_cycle+1] - self.stim.gen_meas_power(meas_name="WRITE0_POWER", + t_initial = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="READ0_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) - t_initial = self.cycle_times[self.write1_cycle] - t_final = self.cycle_times[self.write1_cycle+1] - self.stim.gen_meas_power(meas_name="WRITE1_POWER", + t_initial = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="READ1_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) - t_initial = self.cycle_times[self.read0_cycle] - t_final = self.cycle_times[self.read0_cycle+1] - self.stim.gen_meas_power(meas_name="READ0_POWER", + def write_delay_measures_write_port(self, port): + """ + Write the measure statements to quantify the power results for a write port. + """ + # add measure statements for power + t_initial = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["write0_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="WRITE0_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) - t_initial = self.cycle_times[self.read1_cycle] - t_final = self.cycle_times[self.read1_cycle+1] - self.stim.gen_meas_power(meas_name="READ1_POWER", + t_initial = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]] + t_final = self.cycle_times[self.measure_cycles["write1_{0}".format(port)]+1] + self.stim.gen_meas_power(meas_name="WRITE1_POWER{0}".format(port), t_initial=t_initial, t_final=t_final) + def write_delay_measures(self): + """ + Write the measure statements to quantify the delay and power results for all targeted ports. + """ + self.sf.write("\n* Measure statements for delay and power\n") + + # Output some comments to aid where cycles start and + # what is happening + for comment in self.cycle_comments: + self.sf.write("* {}\n".format(comment)) + + for read_port in self.targ_read_ports: + self.write_delay_measures_read_port(read_port) + for write_port in self.targ_write_ports: + self.write_delay_measures_write_port(write_port) + def write_power_measures(self): """ Write the measure statements to quantify the leakage power only. @@ -275,7 +302,7 @@ class delay(): t_initial=t_initial, t_final=t_final) - def find_feasible_period(self): + def find_feasible_period_one_port(self, port): """ Uses an initial period and finds a feasible period before we run the binary search algorithm to find min period. We check if @@ -283,34 +310,98 @@ class delay(): double the period until we find a valid period to use as a starting point. """ - + debug.check(port in self.read_ports, "Characterizer requires a read port to determine a period.") + #Adding this as a sanity check for editing this function later. This function assumes period has been set previously + debug.check(self.period > 0, "Initial starting period not defined") feasible_period = float(tech.spice["feasible_period"]) - time_out = 8 + #feasible_period = float(2.5)#What happens if feasible starting point is wrong? + time_out = 9 while True: - debug.info(1, "Trying feasible period: {0}ns".format(feasible_period)) time_out -= 1 - if (time_out <= 0): debug.error("Timed out, could not find a feasible period.",2) + + #Clear any write target ports and set read port + self.targ_write_ports = [] + self.targ_read_ports = [port] + success = False + + debug.info(1, "Trying feasible period: {0}ns on Port {1}".format(feasible_period, port)) self.period = feasible_period (success, results)=self.run_delay_simulation() + #Clear these target ports after simulation + self.targ_read_ports = [] + if not success: feasible_period = 2 * feasible_period - continue - feasible_delay_lh = results["delay_lh"] - feasible_slew_lh = results["slew_lh"] - feasible_delay_hl = results["delay_hl"] - feasible_slew_hl = results["slew_hl"] + break + feasible_delay_lh = results["delay_lh{0}".format(port)] + feasible_delay_hl = results["delay_hl{0}".format(port)] + feasible_slew_lh = results["slew_lh{0}".format(port)] + feasible_slew_hl = results["slew_hl{0}".format(port)] delay_str = "feasible_delay {0:.4f}ns/{1:.4f}ns".format(feasible_delay_lh, feasible_delay_hl) slew_str = "slew {0:.4f}ns/{1:.4f}ns".format(feasible_slew_lh, feasible_slew_hl) - debug.info(1, "Found feasible_period: {0}ns {1} {2} ".format(feasible_period, + debug.info(2, "feasible_period passed for Port {3}: {0}ns {1} {2} ".format(feasible_period, delay_str, - slew_str)) - self.period = feasible_period - return (feasible_delay_lh, feasible_delay_hl) - + slew_str, + port)) + #Add feasible delays of port to dict + #feasible_delays_lh[port] = feasible_delay_lh + #feasible_delays_hl[port] = feasible_delay_hl + + if success: + debug.info(1, "Found feasible_period: {0}ns".format(feasible_period)) + self.period = feasible_period + return (feasible_delay_lh, feasible_delay_hl) + def find_feasible_period(self): + """ + Loops through all read ports determining the feasible period and collecting + delay information from each port. + """ + feasible_delays_lh = {} + feasible_delays_hl = {} + self.period = float(tech.spice["feasible_period"]) + + #Get initial feasible period from first port + (feasible_delays_lh[0], feasible_delays_hl[0]) = self.find_feasible_period_one_port(self.read_ports[0]) + previous_period = self.period + + + #Loops through all the ports checks if the feasible period works. Everything restarts it if does not. + #Write ports do not produce delays which is why they are not included here. + i = 1 + while i < len(self.read_ports): + port = self.read_ports[i] + (feasible_delays_lh[port], feasible_delays_hl[port]) = self.find_feasible_period_one_port(port) + #Function sets the period. Restart the entire process if period changes to collect accurate delays + if self.period > previous_period: + i = 0 + else: + i+=1 + previous_period = self.period + return (feasible_delays_lh, feasible_delays_hl) + + + def parse_values(self, values_names, mult = 1.0): + """Parse multiple values in the timing output file. Optional multiplier.""" + values = [] + all_values_floats = True + for vname in values_names: + #ngspice converts all measure characters to lowercase, not tested on other sims + value = parse_spice_list("timing", vname.lower()) + #Check if any of the values fail to parse + if type(value)!=float: + all_values_floats = False + values.append(value) + + #Apply Multiplier only if all values are floats. Let other check functions handle this error. + if all_values_floats: + return {values_names[i]:values[i]*mult for i in range(len(values))} + else: + return {values_names[i]:values[i] for i in range(len(values))} + def run_delay_simulation(self): """ This tries to simulate a period and checks if the result works. If @@ -318,37 +409,38 @@ class delay(): works on the trimmed netlist by default, so powers do not include leakage of all cells. """ - + result = {} # Checking from not data_value to data_value self.write_delay_stimulus() self.stim.run_sim() - delay_hl = parse_spice_list("timing", "delay_hl") - delay_lh = parse_spice_list("timing", "delay_lh") - slew_hl = parse_spice_list("timing", "slew_hl") - slew_lh = parse_spice_list("timing", "slew_lh") - delays = (delay_hl, delay_lh, slew_hl, slew_lh) - - read0_power=parse_spice_list("timing", "read0_power") - write0_power=parse_spice_list("timing", "write0_power") - read1_power=parse_spice_list("timing", "read1_power") - write1_power=parse_spice_list("timing", "write1_power") - - if not self.check_valid_delays(delays): - return (False,{}) + + #Loop through all targeted ports and collect delays and powers. + #Too much duplicate code here. Try reducing + for port in self.targ_read_ports: + delay_names = ["delay_hl{0}".format(port), "delay_lh{0}".format(port), + "slew_hl{0}".format(port), "slew_lh{0}".format(port)] + delays = self.parse_values(delay_names, 1e9) # scale delays to ns + if not self.check_valid_delays((delays[delay_names[0]],delays[delay_names[1]],delays[delay_names[2]],delays[delay_names[3]])): + return (False,{}) + result.update(delays) - # For debug, you sometimes want to inspect each simulation. - #key=raw_input("press return to continue") - - # Scale results to ns and mw, respectively - result = { "delay_hl" : delay_hl*1e9, - "delay_lh" : delay_lh*1e9, - "slew_hl" : slew_hl*1e9, - "slew_lh" : slew_lh*1e9, - "read0_power" : read0_power*1e3, - "read1_power" : read1_power*1e3, - "write0_power" : write0_power*1e3, - "write1_power" : write1_power*1e3} + power_names = ["read0_power{0}".format(port), "read1_power{0}".format(port)] + powers = self.parse_values(power_names, 1e3) # scale power to mw + #Check that power parsing worked. + for name, power in powers.items(): + if type(power)!=float: + debug.error("Failed to Parse Power Values:\n\t\t{0}".format(powers),1) #Printing the entire dict looks bad. + result.update(powers) + + for port in self.targ_write_ports: + power_names = ["write0_power{0}".format(port), "write1_power{0}".format(port)] + powers = self.parse_values(power_names, 1e3) # scale power to mw + #Check that power parsing worked. + for name, power in powers.items(): + if type(power)!=float: + debug.error("Failed to Parse Power Values:\n\t\t{0}".format(powers),1) #Printing the entire dict looks bad. + result.update(powers) # The delay is from the negative edge for our SRAM return (True,result) @@ -359,18 +451,21 @@ class delay(): This simulates a disabled SRAM to get the leakage power when it is off. """ - + debug.info(1, "Performing leakage power simulations.") self.write_power_stimulus(trim=False) self.stim.run_sim() leakage_power=parse_spice_list("timing", "leakage_power") debug.check(leakage_power!="Failed","Could not measure leakage power.") - + debug.info(1, "Leakage power of full array is {0} mW".format(leakage_power*1e3)) + #debug + #sys.exit(1) self.write_power_stimulus(trim=True) self.stim.run_sim() trim_leakage_power=parse_spice_list("timing", "leakage_power") debug.check(trim_leakage_power!="Failed","Could not measure leakage power.") - + debug.info(1, "Leakage power of trimmed array is {0} mW".format(trim_leakage_power*1e3)) + # For debug, you sometimes want to inspect each simulation. #key=raw_input("press return to continue") return (leakage_power*1e3, trim_leakage_power*1e3) @@ -389,11 +484,7 @@ class delay(): delays_str, slews_str)) return False - # Scale delays to ns (they previously could have not been floats) - delay_hl *= 1e9 - delay_lh *= 1e9 - slew_hl *= 1e9 - slew_lh *= 1e9 + delays_str = "delay_hl={0} delay_lh={1}".format(delay_hl, delay_lh) slews_str = "slew_hl={0} slew_lh={1}".format(slew_hl,slew_lh) if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period: @@ -408,87 +499,102 @@ class delay(): return True + def find_min_period(self, feasible_delays_lh, feasible_delays_hl): + """ + Determine the minimum period for all ports. + """ - def find_min_period(self, feasible_delay_lh, feasible_delay_hl): + feasible_period = ub_period = self.period + lb_period = 0.0 + target_period = 0.5 * (ub_period + lb_period) + + #Find the minimum period for all ports. Start at one port and perform binary search then use that delay as a starting position. + #For testing purposes, only checks read ports. + for port in self.read_ports: + target_period = self.find_min_period_one_port(feasible_delays_lh, feasible_delays_hl, port, lb_period, ub_period, target_period) + #The min period of one port becomes the new lower bound. Reset the upper_bound. + lb_period = target_period + ub_period = feasible_period + + #Clear the target ports before leaving + self.targ_read_ports = [] + self.targ_write_ports = [] + return target_period + + def find_min_period_one_port(self, feasible_delays_lh, feasible_delays_hl, port, lb_period, ub_period, target_period): """ Searches for the smallest period with output delays being within 5% of - long period. + long period. For the current logic to characterize multiport, bound are required as an input. """ - previous_period = ub_period = self.period - lb_period = 0.0 - - # Binary search algorithm to find the min period (max frequency) of design + #previous_period = ub_period = self.period + #ub_period = self.period + #lb_period = 0.0 + #target_period = 0.5 * (ub_period + lb_period) + + # Binary search algorithm to find the min period (max frequency) of input port time_out = 25 + self.targ_read_ports = [port] while True: time_out -= 1 if (time_out <= 0): debug.error("Timed out, could not converge on minimum period.",2) - target_period = 0.5 * (ub_period + lb_period) self.period = target_period - debug.info(1, "MinPeriod Search: {0}ns (ub: {1} lb: {2})".format(target_period, + debug.info(1, "MinPeriod Search Port {3}: {0}ns (ub: {1} lb: {2})".format(target_period, ub_period, - lb_period)) + lb_period, + port)) - if self.try_period(feasible_delay_lh, feasible_delay_hl): + if self.try_period(feasible_delays_lh, feasible_delays_hl): ub_period = target_period else: lb_period = target_period if relative_compare(ub_period, lb_period, error_tolerance=0.05): - # ub_period is always feasible + # ub_period is always feasible. When done with a port, set the target period of the next port as the lower bound + # and reset the upperbound return ub_period + #target_period = lb_period = ub_period + #ub_period = previous_period + #break + + #Update target + target_period = 0.5 * (ub_period + lb_period) - - def try_period(self, feasible_delay_lh, feasible_delay_hl): + + def try_period(self, feasible_delays_lh, feasible_delays_hl): """ This tries to simulate a period and checks if the result works. If it does and the delay is within 5% still, it returns True. """ + # Run Delay simulation but Power results not used. + (success, results) = self.run_delay_simulation() + if not success: + return False + + #Check the values of target readwrite and read ports. Write ports do not produce delays in this current version + for port in self.targ_read_ports: + delay_hl = results["delay_hl{0}".format(port)] + delay_lh = results["delay_lh{0}".format(port)] + slew_hl = results["slew_hl{0}".format(port)] + slew_lh = results["slew_lh{0}".format(port)] - # Checking from not data_value to data_value - self.write_delay_stimulus() - self.stim.run_sim() - delay_hl = parse_spice_list("timing", "delay_hl") - delay_lh = parse_spice_list("timing", "delay_lh") - slew_hl = parse_spice_list("timing", "slew_hl") - slew_lh = parse_spice_list("timing", "slew_lh") - # if it failed or the read was longer than a period - if type(delay_hl)!=float or type(delay_lh)!=float or type(slew_lh)!=float or type(slew_hl)!=float: - debug.info(2,"Invalid measures: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, - delay_hl, - delay_lh, - slew_hl, - slew_lh)) - return False - delay_hl *= 1e9 - delay_lh *= 1e9 - slew_hl *= 1e9 - slew_lh *= 1e9 - if delay_hl>self.period or delay_lh>self.period or slew_hl>self.period or slew_lh>self.period: - debug.info(2,"Too long delay/slew: Period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, - delay_hl, - delay_lh, - slew_hl, - slew_lh)) - return False - else: - if not relative_compare(delay_lh,feasible_delay_lh,error_tolerance=0.05): - debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delay_lh)) + if not relative_compare(delay_lh,feasible_delays_lh[port],error_tolerance=0.05): + debug.info(2,"Delay too big {0} vs {1}".format(delay_lh,feasible_delays_lh[port])) return False - elif not relative_compare(delay_hl,feasible_delay_hl,error_tolerance=0.05): - debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delay_hl)) + elif not relative_compare(delay_hl,feasible_delays_hl[port],error_tolerance=0.05): + debug.info(2,"Delay too big {0} vs {1}".format(delay_hl,feasible_delays_hl[port])) return False + #key=raw_input("press return to continue") - #key=raw_input("press return to continue") - - debug.info(2,"Successful period {0}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, - delay_hl, - delay_lh, - slew_hl, - slew_lh)) + debug.info(2,"Successful period {0}, Port {5}, delay_hl={1}ns, delay_lh={2}ns slew_hl={3}ns slew_lh={4}ns".format(self.period, + delay_hl, + delay_lh, + slew_hl, + slew_lh, + port)) return True def set_probe(self,probe_address, probe_data): @@ -527,11 +633,14 @@ class delay(): """ Main function to characterize an SRAM for a table. Computes both delay and power characterization. """ - # Data structure for all the characterization values - char_data = {} - self.set_probe(probe_address, probe_data) - + + self.create_port_names() + + self.create_char_data_dict() + + self.load=max(loads) + self.slew=max(slews) # This is for debugging a full simulation # debug.info(0,"Debug simulation running...") # target_period=50.0 @@ -542,31 +651,49 @@ class delay(): # self.try_period(target_period, feasible_delay_lh, feasible_delay_hl) # sys.exit(1) - + #For debugging, skips characterization and returns dummy values. + # char_data = self.char_data + # i = 1.0 + # for slew in slews: + # for load in loads: + # for k,v in char_data.items(): + # char_data[k].append(i) + # i+=1.0 + # char_data["min_period"] = i + # char_data["leakage_power"] = i+1.0 + # return char_data + # 1) Find a feasible period and it's corresponding delays using the trimmed array. - self.load=max(loads) - self.slew=max(slews) - (feasible_delay_lh, feasible_delay_hl) = self.find_feasible_period() - debug.check(feasible_delay_lh>0,"Negative delay may not be possible") - debug.check(feasible_delay_hl>0,"Negative delay may not be possible") + (feasible_delays_lh, feasible_delays_hl) = self.find_feasible_period() + #Check all the delays + for k,v in feasible_delays_lh.items(): + debug.check(v>0,"Negative delay may not be possible") + for k,v in feasible_delays_hl.items(): + debug.check(v>0,"Negative delay may not be possible") + # 2) Finds the minimum period without degrading the delays by X% self.set_load_slew(max(loads),max(slews)) - min_period = self.find_min_period(feasible_delay_lh, feasible_delay_hl) + min_period = self.find_min_period(feasible_delays_lh, feasible_delays_hl) debug.check(type(min_period)==float,"Couldn't find minimum period.") - debug.info(1, "Min Period: {0}n with a delay of {1} / {2}".format(min_period, feasible_delay_lh, feasible_delay_hl)) - char_data["min_period"] = round_time(min_period) - - # Make a list for each type of measurement to append results to - for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power", - "read1_power", "write0_power", "write1_power", "leakage_power"]: - char_data[m]=[] + debug.info(1, "Min Period Found: {0}ns".format(min_period)) + self.char_data["min_period"] = round_time(min_period) # 3) Find the leakage power of the trimmmed and UNtrimmed arrays. (full_array_leakage, trim_array_leakage)=self.run_power_simulation() - char_data["leakage_power"]=full_array_leakage - + self.char_data["leakage_power"]=full_array_leakage + leakage_offset = full_array_leakage - trim_array_leakage + # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs. + self.simulate_loads_and_slews(slews, loads, leakage_offset) + + return self.char_data + + def simulate_loads_and_slews(self, slews, loads, leakage_offset): + """Simulate all specified output loads and input slews pairs""" + #Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways. + self.targ_read_ports = self.read_ports + self.targ_write_ports = self.write_ports for slew in slews: for load in loads: self.set_load_slew(load,slew) @@ -576,109 +703,123 @@ class delay(): for k,v in delay_results.items(): if "power" in k: # Subtract partial array leakage and add full array leakage for the power measures - char_data[k].append(v - trim_array_leakage + full_array_leakage) + self.char_data[k].append(v + leakage_offset) else: - char_data[k].append(v) - - - - return char_data - - - - def add_data(self, data): + self.char_data[k].append(v) + + def add_data(self, data, port): """ Add the array of data values """ debug.check(len(data)==self.word_size, "Invalid data word size.") + debug.check(port < len(self.data_values), "Port number cannot index data values.") index = 0 for c in data: if c=="0": - self.data_values[index].append(0) + self.data_values[port][index].append(0) elif c=="1": - self.data_values[index].append(1) + self.data_values[port][index].append(1) else: debug.error("Non-binary data string",1) index += 1 - def add_address(self, address): + def add_address(self, address, port): """ Add the array of address values """ debug.check(len(address)==self.addr_size, "Invalid address size.") index = 0 for c in address: if c=="0": - self.addr_values[index].append(0) + self.addr_values[port][index].append(0) elif c=="1": - self.addr_values[index].append(1) + self.addr_values[port][index].append(1) else: debug.error("Non-binary address string",1) index += 1 - def add_noop(self, comment, address, data): - """ Add the control values for a read cycle. """ - self.cycle_comments.append("Cycle {0:2d}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_times), + def add_noop_one_port(self, address, data, port): + """ Add the control values for a noop to a single port. """ + #This is to be used as a helper function for the other add functions. Cycle and comments are omitted. + self.add_control_one_port(port, "noop") + if port in self.write_ports: + self.add_data(data,port) + self.add_address(address, port) + + def add_noop_all_ports(self, comment, address, data): + """ Add the control values for a noop to all ports. """ + self.cycle_comments.append("Cycle {0:2d}\tPort All\t{1:5.2f}ns:\t{2}".format(len(self.cycle_times), self.t_current, comment)) self.cycle_times.append(self.t_current) self.t_current += self.period - self.web_values.append(1) - self.csb_values.append(1) - - self.add_data(data) - self.add_address(address) + + for port in range(self.total_port_num): + self.add_noop_one_port(address, data, port) - def add_read(self, comment, address, data): + def add_read(self, comment, address, data, port): """ Add the control values for a read cycle. """ - self.cycle_comments.append("Cycle {0:2d}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), + debug.check(port in self.read_ports, "Cannot add read cycle to a write port.") + self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), self.t_current, - comment)) + comment, + port)) + self.cycle_times.append(self.t_current) + self.t_current += self.period + self.add_control_one_port(port, "read") + + #If the port is also a readwrite then add data. + if port in self.write_ports: + self.add_data(data,port) + self.add_address(address, port) + + #This value is hard coded here. Possibly change to member variable or set in add_noop_one_port + noop_data = "0"*self.word_size + #Add noops to all other ports. + for unselected_port in range(self.total_port_num): + if unselected_port != port: + self.add_noop_one_port(address, noop_data, unselected_port) + + def add_write(self, comment, address, data, port): + """ Add the control values for a write cycle. """ + debug.check(port in self.write_ports, "Cannot add read cycle to a read port.") + self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), + self.t_current, + comment, + port)) self.cycle_times.append(self.t_current) self.t_current += self.period - self.web_values.append(1) - self.csb_values.append(0) - - self.add_data(data) - self.add_address(address) + self.add_control_one_port(port, "write") + self.add_data(data,port) + self.add_address(address,port) + #This value is hard coded here. Possibly change to member variable or set in add_noop_one_port + noop_data = "0"*self.word_size + #Add noops to all other ports. + for unselected_port in range(self.total_port_num): + if unselected_port != port: + self.add_noop_one_port(address, noop_data, unselected_port) + + def add_control_one_port(self, port, op): + """Appends control signals for operation to a given port""" + #Determine values to write to port + web_val = 1 + csb_val = 1 + if op == "read": + csb_val = 0 + elif op == "write": + csb_val = 0 + web_val = 0 + elif op != "noop": + debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port,op),1) + #Append the values depending on the type of port + self.csb_values[port].append(csb_val) + #If port is in both lists, add rw control signal. Condition indicates its a RW port. + if port < len(self.web_values): + self.web_values[port].append(web_val) - def add_write(self, comment, address, data): - """ Add the control values for a read cycle. """ - self.cycle_comments.append("Cycle {0:2d}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments), - self.t_current, - comment)) - self.cycle_times.append(self.t_current) - self.t_current += self.period - - self.web_values.append(0) - self.csb_values.append(0) - - self.add_data(data) - self.add_address(address) - - def create_test_cycles(self): - """Returns a list of key time-points [ns] of the waveform (each rising edge) - of the cycles to do a timing evaluation. The last time is the end of the simulation - and does not need a rising edge.""" - - # Start at time 0 - self.t_current = 0 - - # Cycle times (positive edge) with comment - self.cycle_comments = [] - self.cycle_times = [] - - # Control logic signals each cycle - self.web_values = [] - self.csb_values = [] - - # Address and data values for each address/data bit - self.data_values=[] - for i in range(self.word_size): - self.data_values.append([]) - self.addr_values=[] - for i in range(self.addr_size): - self.addr_values.append([]) + def gen_test_cycles_one_port(self, read_port, write_port): + """Intended but not implemented: Returns a list of key time-points [ns] of the waveform (each rising edge) + of the cycles to do a timing evaluation of a single port. Current: Values overwritten for multiple calls""" # Create the inverse address for a scratch address inverse_address = "" @@ -694,51 +835,119 @@ class delay(): data_ones = "1"*self.word_size data_zeros = "0"*self.word_size - self.add_noop("Idle cycle (no positive clock edge)", + if self.t_current == 0: + self.add_noop_all_ports("Idle cycle (no positive clock edge)", inverse_address, data_zeros) - + self.add_write("W data 1 address 0..00", - inverse_address,data_ones) + inverse_address,data_ones,write_port) self.add_write("W data 0 address 11..11 to write value", - self.probe_address,data_zeros) - self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure + self.probe_address,data_zeros,write_port) + self.measure_cycles["write0_{0}".format(write_port)] = len(self.cycle_times)-1 + #self.write0_cycle=len(self.cycle_times)-1 # Remember for power measure # This also ensures we will have a H->L transition on the next read self.add_read("R data 1 address 00..00 to set DOUT caps", - inverse_address,data_zeros) + inverse_address,data_zeros,read_port) self.add_read("R data 0 address 11..11 to check W0 worked", - self.probe_address,data_zeros) - self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure + self.probe_address,data_zeros,read_port) + self.measure_cycles["read0_{0}".format(read_port)] = len(self.cycle_times)-1 + #self.read0_cycle=len(self.cycle_times)-1 # Remember for power measure - self.add_noop("Idle cycle (if read takes >1 cycle)", + self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)", inverse_address,data_zeros) - self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure + #Does not seem like is is used anywhere commenting out for now. + #self.idle_cycle=len(self.cycle_times)-1 # Remember for power measure self.add_write("W data 1 address 11..11 to write value", - self.probe_address,data_ones) - self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure + self.probe_address,data_ones,write_port) + self.measure_cycles["write1_{0}".format(write_port)] = len(self.cycle_times)-1 + #self.write1_cycle=len(self.cycle_times)-1 # Remember for power measure self.add_write("W data 0 address 00..00 to clear DIN caps", - inverse_address,data_zeros) + inverse_address,data_zeros,write_port) # This also ensures we will have a L->H transition on the next read self.add_read("R data 0 address 00..00 to clear DOUT caps", - inverse_address,data_zeros) + inverse_address,data_zeros,read_port) self.add_read("R data 1 address 11..11 to check W1 worked", + self.probe_address,data_zeros,read_port) + self.measure_cycles["read1_{0}".format(read_port)] = len(self.cycle_times)-1 + #self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure + + self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))", self.probe_address,data_zeros) - self.read1_cycle=len(self.cycle_times)-1 # Remember for power measure - - self.add_noop("Idle cycle (if read takes >1 cycle))", - self.probe_address,data_zeros) + + def get_available_port(self,get_read_port): + """Returns the first accessible read or write port. """ + if get_read_port and len(self.read_ports) > 0: + return self.read_ports[0] + elif not get_read_port and len(self.write_ports) > 0: + return self.write_ports[0] + return None + + def create_test_cycles(self): + """Returns a list of key time-points [ns] of the waveform (each rising edge) + of the cycles to do a timing evaluation. The last time is the end of the simulation + and does not need a rising edge.""" + #Using this requires setting at least one port to target for simulation. + if len(self.targ_write_ports) == 0 and len(self.targ_read_ports) == 0: + debug.error("No ports selected for characterization.",1) + + # Start at time 0 + self.t_current = 0 + # Cycle times (positive edge) with comment + self.cycle_comments = [] + self.cycle_times = [] + self.measure_cycles = {} + # Control signals for ports. These are not the final signals and will likely be changed later. + #write enable bar for readwrite ports to control read or write + self.web_values = [[] for i in range(self.readwrite_port_num)] + #csb represents a basic "enable" signal that all ports have. + self.csb_values = [[] for i in range(self.total_port_num)] + + # Address and data values for each address/data bit. A dict of 3d lists of size #ports x bits x cycles. + self.data_values=[[[] for i in range(self.addr_size)]]*len(self.write_ports) + self.addr_values=[[[] for i in range(self.addr_size)]]*self.total_port_num + + #Get any available read/write port in case only a single write or read ports is being characterized. + cur_read_port = self.get_available_port(get_read_port=True) + cur_write_port = self.get_available_port(get_read_port=False) + + #These checks should be superceded by check_arguments which should have been called earlier, so this is a double check. + debug.check(cur_read_port != None, "Characterizer requires at least 1 read port") + debug.check(cur_write_port != None, "Characterizer requires at least 1 write port") + + #Characterizing the remaining target ports. Not the final design. + write_pos = 0 + read_pos = 0 + while True: + #Exit when all ports have been characterized + if write_pos >= len(self.targ_write_ports) and read_pos >= len(self.targ_read_ports): + break + + #Select new write and/or read ports for the next cycle. Use previous port if none remaining. + if write_pos < len(self.targ_write_ports): + cur_write_port = self.targ_write_ports[write_pos] + write_pos+=1 + if read_pos < len(self.targ_read_ports): + cur_read_port = self.targ_read_ports[read_pos] + read_pos+=1 + + #Add test cycle of read/write port pair. One port could have been used already, but the other has not. + self.gen_test_cycles_one_port(cur_read_port, cur_write_port) def analytical_delay(self,sram, slews, loads): - """ Just return the analytical model results for the SRAM. + """ Return the analytical model results for the SRAM. """ + debug.check(OPTS.num_rw_ports < 2 and OPTS.num_w_ports < 1 and OPTS.num_r_ports < 1 , + "Analytical characterization does not currently support multiport.") + delay_lh = [] delay_hl = [] slew_lh = [] @@ -761,35 +970,72 @@ class delay(): debug.info(1,"Leakage Power: {0} mW".format(power.leakage)) data = {"min_period": 0, - "delay_lh": delay_lh, - "delay_hl": delay_hl, - "slew_lh": slew_lh, - "slew_hl": slew_hl, - "read0_power": power.dynamic, - "read1_power": power.dynamic, - "write0_power": power.dynamic, - "write1_power": power.dynamic, + "delay_lh0": delay_lh, + "delay_hl0": delay_hl, + "slew_lh0": slew_lh, + "slew_hl0": slew_hl, + "read0_power0": power.dynamic, + "read1_power0": power.dynamic, + "write0_power0": power.dynamic, + "write1_power0": power.dynamic, "leakage_power": power.leakage } return data def gen_data(self): """ Generates the PWL data inputs for a simulation timing test. """ - for i in range(self.word_size): - sig_name="DIN[{0}]".format(i) - self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[i], self.period, self.slew, 0.05) + for write_port in self.write_ports: + for i in range(self.word_size): + sig_name="DIN{0}[{1}] ".format(write_port, i) + self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[write_port][i], self.period, self.slew, 0.05) def gen_addr(self): """ Generates the address inputs for a simulation timing test. This alternates between all 1's and all 0's for the address. """ - for i in range(self.addr_size): - sig_name = "A[{0}]".format(i) - self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[i], self.period, self.slew, 0.05) - + for port in range(self.total_port_num): + for i in range(self.addr_size): + sig_name = "A{0}[{1}]".format(port,i) + self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][i], self.period, self.slew, 0.05) def gen_control(self): """ Generates the control signals """ - self.stim.gen_pwl("csb", self.cycle_times, self.csb_values, self.period, self.slew, 0.05) - self.stim.gen_pwl("web", self.cycle_times, self.web_values, self.period, self.slew, 0.05) + for port in range(self.total_port_num): + self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05) + + for readwrite_port in range(self.readwrite_port_num): + self.stim.gen_pwl("WEB{0}".format(readwrite_port), self.cycle_times, self.web_values[readwrite_port], self.period, self.slew, 0.05) + + + def create_port_names(self): + """Generates the port names to be used in characterization and sets default simulation target ports""" + self.write_ports = [] + self.read_ports = [] + self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + + #save a member variable to avoid accessing global. readwrite ports have different control signals. + self.readwrite_port_num = OPTS.num_rw_ports + + #Generate the port names. readwrite ports are required to be added first for this to work. + for readwrite_port_num in range(OPTS.num_rw_ports): + self.read_ports.append(readwrite_port_num) + self.write_ports.append(readwrite_port_num) + #This placement is intentional. It makes indexing input data easier. See self.data_values + for write_port_num in range(OPTS.num_rw_ports, OPTS.num_rw_ports+OPTS.num_w_ports): + self.write_ports.append(write_port_num) + for read_port_num in range(OPTS.num_rw_ports+OPTS.num_w_ports, OPTS.num_rw_ports+OPTS.num_w_ports+OPTS.num_r_ports): + self.read_ports.append(read_port_num) + + #Set the default target ports for simulation. Default is all the ports. + self.targ_read_ports = self.read_ports + self.targ_write_ports = self.write_ports + + def create_char_data_dict(self): + """Make a dict of lists for each type of measurement to append results to""" + #Making this a member variable may not be the best option, but helps reduce code clutter + self.char_data = {} + for port in range(self.total_port_num): + for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power", + "read1_power", "write0_power", "write1_power"]: + self.char_data ["{0}{1}".format(m,port)]=[] \ No newline at end of file diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 2ac65513..9f04fd7f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -12,18 +12,43 @@ class lib: """ lib file generation.""" def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay): + #Temporary Workaround to here to set num of ports. Crashes if set in config file. + #OPTS.num_rw_ports = 2 + #OPTS.num_r_ports = 1 + #OPTS.num_w_ports = 1 + self.out_dir = out_dir self.sram = sram self.sp_file = sp_file self.use_model = use_model - + self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later. + self.prepare_tables() self.create_corners() self.characterize_corners() - + def gen_port_names(self): + """Generates the port names to be written to the lib file""" + #This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here. + self.write_ports = [] + self.read_ports = [] + self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + + #save a member variable to avoid accessing global. readwrite ports have different control signals. + self.readwrite_port_num = OPTS.num_rw_ports + + #Generate the port names. readwrite ports are required to be added first for this to work. + for readwrite_port_num in range(OPTS.num_rw_ports): + self.read_ports.append(readwrite_port_num) + self.write_ports.append(readwrite_port_num) + #This placement is intentional. It makes indexing input data easier. See self.data_values + for read_port_num in range(OPTS.num_rw_ports, OPTS.num_r_ports): + self.read_ports.append(read_port_num) + for write_port_num in range(OPTS.num_rw_ports+OPTS.num_r_ports, OPTS.num_w_ports): + self.write_ports.append(write_port_num) + def prepare_tables(self): """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes @@ -85,13 +110,14 @@ class lib: self.write_header() - self.write_data_bus() - - self.write_addr_bus() - - self.write_control_pins() - - self.write_clk() + #Loop over all readwrite ports. This is debugging. Will change later. + for port in range(self.total_port_num): + #set the read and write port as inputs. + self.write_data_bus(port) + self.write_addr_bus(port) + self.write_control_pins(port) #need to split this into sram and port control signals + + self.write_clk_timing_power() self.write_footer() @@ -127,9 +153,14 @@ class lib: self.lib.write(" dont_touch : true;\n") self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height)) + #Build string of all control signals. This is subject to change once control signals finalized. + control_str = 'CSb0' #assume at least 1 port + for i in range(1, self.total_port_num): + control_str += ' & CSb{0}'.format(i) + # Leakage is included in dynamic when macro is enabled self.lib.write(" leakage_power () {\n") - self.lib.write(" when : \"CSb\";\n") + self.lib.write(" when : \"{0}\";\n".format(control_str)) self.lib.write(" value : {};\n".format(self.char_results["leakage_power"])) self.lib.write(" }\n") self.lib.write(" cell_leakage_power : {};\n".format(0)) @@ -295,65 +326,72 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") - - - def write_data_bus(self): + def write_data_bus_output(self, read_port): """ Adds data bus timing results.""" - self.lib.write(" bus(DIN){\n") + self.lib.write(" bus(DOUT{0}){{\n".format(read_port)) self.lib.write(" bus_type : DATA; \n") - self.lib.write(" direction : in; \n") - # This is conservative, but limit to range that we characterized. - self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads))) - self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads))) - self.lib.write(" memory_write(){ \n") - self.lib.write(" address : ADDR; \n") - self.lib.write(" clocked_on : clk; \n") - self.lib.write(" }\n") - - self.lib.write(" bus(DOUT){\n") - self.lib.write(" bus_type : DATA; \n") - self.lib.write(" direction : out; \n") + self.lib.write(" direction : output; \n") # This is conservative, but limit to range that we characterized. self.lib.write(" max_capacitance : {0}; \n".format(max(self.loads))) self.lib.write(" min_capacitance : {0}; \n".format(min(self.loads))) self.lib.write(" memory_read(){ \n") - self.lib.write(" address : ADDR; \n") + self.lib.write(" address : ADDR{0}; \n".format(read_port)) self.lib.write(" }\n") - self.lib.write(" pin(DOUT[{0}:0]){{\n".format(self.sram.word_size - 1)) + self.lib.write(" pin(DOUT{1}[{0}:0]){{\n".format(self.sram.word_size - 1, read_port)) self.write_FF_setuphold() self.lib.write(" timing(){ \n") self.lib.write(" timing_sense : non_unate; \n") self.lib.write(" related_pin : \"clk\"; \n") self.lib.write(" timing_type : rising_edge; \n") self.lib.write(" cell_rise(CELL_TABLE) {\n") - self.write_values(self.char_results["delay_lh"],len(self.loads)," ") + self.write_values(self.char_results["delay_lh{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # rise delay self.lib.write(" cell_fall(CELL_TABLE) {\n") - self.write_values(self.char_results["delay_hl"],len(self.loads)," ") + self.write_values(self.char_results["delay_hl{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # fall delay self.lib.write(" rise_transition(CELL_TABLE) {\n") - self.write_values(self.char_results["slew_lh"],len(self.loads)," ") + self.write_values(self.char_results["slew_lh{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # rise trans self.lib.write(" fall_transition(CELL_TABLE) {\n") - self.write_values(self.char_results["slew_hl"],len(self.loads)," ") + self.write_values(self.char_results["slew_hl{0}".format(read_port)],len(self.loads)," ") self.lib.write(" }\n") # fall trans self.lib.write(" }\n") # timing self.lib.write(" }\n") # pin self.lib.write(" }\n\n") # bus + def write_data_bus_input(self, write_port): + """ Adds data bus timing results.""" - def write_addr_bus(self): + self.lib.write(" bus(DIN{0}){{\n".format(write_port)) + self.lib.write(" bus_type : DATA; \n") + self.lib.write(" direction : input; \n") + # This is conservative, but limit to range that we characterized. + self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) + self.lib.write(" memory_write(){ \n") + self.lib.write(" address : ADDR{0}; \n".format(write_port)) + self.lib.write(" clocked_on : clk; \n") + self.lib.write(" }\n") + self.lib.write(" }\n") + + def write_data_bus(self, port): + """ Adds data bus timing results.""" + if port in self.write_ports: + self.write_data_bus_input(port) + if port in self.read_ports: + self.write_data_bus_output(port) + + def write_addr_bus(self, port): """ Adds addr bus timing results.""" - - self.lib.write(" bus(ADDR){\n") + + self.lib.write(" bus(ADDR{0}){{\n".format(port)) self.lib.write(" bus_type : ADDR; \n") self.lib.write(" direction : input; \n") self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) self.lib.write(" max_transition : {0};\n".format(self.slews[-1])) - self.lib.write(" pin(ADDR[{0}:0])".format(self.sram.addr_size - 1)) + self.lib.write(" pin(ADDR{1}[{0}:0])".format(self.sram.addr_size - 1, port)) self.lib.write("{\n") self.write_FF_setuphold() @@ -361,10 +399,13 @@ class lib: self.lib.write(" }\n\n") - def write_control_pins(self): + def write_control_pins(self, port): """ Adds control pins timing results.""" - - ctrl_pin_names = ["CSb", "OEb", "WEb"] + #The control pins are still to be determined. This is a placeholder for what could be. + ctrl_pin_names = ["CSb{0}".format(port)] + if port in self.write_ports and port in self.read_ports: + ctrl_pin_names.append("WEb{0}".format(port)) + for i in ctrl_pin_names: self.lib.write(" pin({0})".format(i)) self.lib.write("{\n") @@ -373,8 +414,7 @@ class lib: self.write_FF_setuphold() self.lib.write(" }\n\n") - - def write_clk(self): + def write_clk_timing_power(self): """ Adds clk pin timing results.""" self.lib.write(" pin(clk){\n") @@ -383,41 +423,10 @@ class lib: # FIXME: This depends on the clock buffer size in the control logic self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"])) - # Find the average power of 1 and 0 bits for writes and reads over all loads/slews - # Could make it a table, but this is fine for now. - avg_write_power = np.mean(self.char_results["write1_power"] + self.char_results["write0_power"]) - avg_read_power = np.mean(self.char_results["read1_power"] + self.char_results["read0_power"]) - - # Equally divide read/write power between first and second half of clock period - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!CSb & clk & !WEb\"; \n") - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" }\n") - - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"!CSb & !clk & WEb\"; \n") - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) - self.lib.write(" }\n") - self.lib.write(" }\n") - # Have 0 internal power when disabled, this will be represented as leakage power. - self.lib.write(" internal_power(){\n") - self.lib.write(" when : \"CSb\"; \n") - self.lib.write(" rise_power(scalar){\n") - self.lib.write(" values(\"0\");\n") - self.lib.write(" }\n") - self.lib.write(" fall_power(scalar){\n") - self.lib.write(" values(\"0\");\n") - self.lib.write(" }\n") - self.lib.write(" }\n") + #Add power values for the ports. lib generated with this is not syntactically correct. TODO once + #top level is done. + for port in range(self.total_port_num): + self.add_clk_control_power(port) min_pulse_width = round_time(self.char_results["min_period"])/2.0 min_period = round_time(self.char_results["min_period"]) @@ -443,7 +452,51 @@ class lib: self.lib.write(" }\n") self.lib.write(" }\n") self.lib.write(" }\n") + + def add_clk_control_power(self, port): + """Writes powers under the clock pin group for a specified port""" + #Web added to read/write ports. Likely to change when control logic finished. + web_name = "" + + if port in self.write_ports: + if port in self.read_ports: + web_name = " & !WEb{0}".format(port) + avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"!CSb{0} & clk{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" }\n") + if port in self.read_ports: + if port in self.write_ports: + web_name = " & WEb{0}".format(port) + avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)]) + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"!CSb{0} & !clk{1}\"; \n".format(port, web_name)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0)) + self.lib.write(" }\n") + self.lib.write(" }\n") + + # Have 0 internal power when disabled, this will be represented as leakage power. + self.lib.write(" internal_power(){\n") + self.lib.write(" when : \"CSb{0}\"; \n".format(port)) + self.lib.write(" rise_power(scalar){\n") + self.lib.write(" values(\"0\");\n") + self.lib.write(" }\n") + self.lib.write(" fall_power(scalar){\n") + self.lib.write(" values(\"0\");\n") + self.lib.write(" }\n") + self.lib.write(" }\n") + def compute_delay(self): """ Do the analysis if we haven't characterized the SRAM yet """ if not hasattr(self,"d"): diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py index aaeff0cd..8a515776 100644 --- a/compiler/characterizer/setup_hold.py +++ b/compiler/characterizer/setup_hold.py @@ -3,7 +3,7 @@ import tech from .stimuli import * import debug from .charutils import * -import ms_flop +import dff from globals import OPTS @@ -15,9 +15,9 @@ class setup_hold(): def __init__(self, corner): # This must match the spice model order - self.pins = ["data", "dout", "dout_bar", "clk", "vdd", "gnd"] - self.model_name = "ms_flop" - self.model_location = OPTS.openram_tech + "sp_lib/ms_flop.sp" + self.pins = ["data", "dout", "clk", "vdd", "gnd"] + self.model_name = "dff" + self.model_location = OPTS.openram_tech + "sp_lib/dff.sp" self.period = tech.spice["feasible_period"] debug.info(2,"Feasible period from technology file: {0} ".format(self.period)) @@ -276,17 +276,36 @@ class setup_hold(): HL_setup = [] LH_hold = [] HL_hold = [] + + #For debugging, skips characterization and returns dummy values. + # i = 1.0 + # for self.related_input_slew in related_slews: + # for self.constrained_input_slew in constrained_slews: + # LH_setup.append(i) + # HL_setup.append(i+1.0) + # LH_hold.append(i+2.0) + # HL_hold.append(i+3.0) + # i+=4.0 + + # times = {"setup_times_LH": LH_setup, + # "setup_times_HL": HL_setup, + # "hold_times_LH": LH_hold, + # "hold_times_HL": HL_hold + # } + # return times + + for self.related_input_slew in related_slews: for self.constrained_input_slew in constrained_slews: debug.info(1, "Clock slew: {0} Data slew: {1}".format(self.related_input_slew,self.constrained_input_slew)) LH_setup_time = self.setup_LH_time() - debug.info(1, " Setup Time for low_to_high transistion: {0}".format(LH_setup_time)) + debug.info(1, " Setup Time for low_to_high transition: {0}".format(LH_setup_time)) HL_setup_time = self.setup_HL_time() - debug.info(1, " Setup Time for high_to_low transistion: {0}".format(HL_setup_time)) + debug.info(1, " Setup Time for high_to_low transition: {0}".format(HL_setup_time)) LH_hold_time = self.hold_LH_time() - debug.info(1, " Hold Time for low_to_high transistion: {0}".format(LH_hold_time)) + debug.info(1, " Hold Time for low_to_high transition: {0}".format(LH_hold_time)) HL_hold_time = self.hold_HL_time() - debug.info(1, " Hold Time for high_to_low transistion: {0}".format(HL_hold_time)) + debug.info(1, " Hold Time for high_to_low transition: {0}".format(HL_hold_time)) LH_setup.append(LH_setup_time) HL_setup.append(HL_setup_time) LH_hold.append(LH_hold_time) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 2cca1384..b99aadd4 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -30,18 +30,33 @@ class stimuli(): self.device_models = tech.spice["fet_models"][self.process] - def inst_sram(self, abits, dbits, sram_name): + def inst_sram(self, abits, dbits, port_info, sram_name): """ Function to instatiate an SRAM subckt. """ self.sf.write("Xsram ") - for i in range(dbits): - self.sf.write("DIN[{0}] ".format(i)) - for i in range(abits): - self.sf.write("A[{0}] ".format(i)) - for i in tech.spice["control_signals"]: - self.sf.write("{0} ".format(i)) + + #Un-tuple the port names. This was done to avoid passing them all as arguments. Could be improved still. + #This should be generated from the pin list of the sram... change when multiport pins done. + (total_port_num,readwrite_num,read_ports,write_ports) = port_info + + for write_input in write_ports: + for i in range(dbits): + self.sf.write("DIN{0}[{1}] ".format(write_input, i)) + + for port in range(total_port_num): + for i in range(abits): + self.sf.write("A{0}[{1}] ".format(port,i)) + + #These control signals assume 6t sram i.e. a single readwrite port. If multiple readwrite ports are used then add more + #control signals. Not sure if this is correct, consider a temporary change until control signals for multiport are finalized. + for port in range(total_port_num): + self.sf.write("CSB{0} ".format(port)) + for readwrite_port in range(readwrite_num): + self.sf.write("WEB{0} ".format(readwrite_port)) + self.sf.write("{0} ".format(tech.spice["clk"])) - for i in range(dbits): - self.sf.write("DOUT[{0}] ".format(i)) + for read_output in read_ports: + for i in range(dbits): + self.sf.write("DOUT{0}[{1}] ".format(read_output, i)) self.sf.write("{0} {1} ".format(self.vdd_name, self.gnd_name)) self.sf.write("{0}\n".format(sram_name)) diff --git a/compiler/example_config_freepdk45.py b/compiler/example_config_freepdk45.py index 774d41fb..32655f09 100644 --- a/compiler/example_config_freepdk45.py +++ b/compiler/example_config_freepdk45.py @@ -10,3 +10,10 @@ temperatures = [25] output_path = "temp" output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name) +#Below are some additions to test additional ports on sram +#bitcell = "pbitcell" + +# These are the configuration parameters +#rw_ports = 2 +#r_ports = 2 +#w_ports = 2 diff --git a/compiler/example_config_scn3me_subm.py b/compiler/example_config_scn3me_subm.py index 356b4542..fec65d95 100644 --- a/compiler/example_config_scn3me_subm.py +++ b/compiler/example_config_scn3me_subm.py @@ -9,4 +9,3 @@ temperatures = [ 25 ] output_path = "temp" output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name) - diff --git a/compiler/globals.py b/compiler/globals.py index 7a7d0098..6d5e9b63 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -59,7 +59,7 @@ def parse_args(): OPTS.tech_name = "scmos" # Alias SCMOS to AMI 0.5um if OPTS.tech_name == "scmos": - OPTS.tech_name = "scn3me_subm" + OPTS.tech_name = "scn4m_subm" return (options, args) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f8e76a8b..d6c884a4 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -67,10 +67,21 @@ class bank(design.design): self.DRC_LVS() def add_pins(self): + self.read_index = [] + port_number = 0 + for port in range(OPTS.num_rw_ports): + self.read_index.append("{}".format(port_number)) + port_number += 1 + for port in range(OPTS.num_w_ports): + port_number += 1 + for port in range(OPTS.num_r_ports): + self.read_index.append("{}".format(port_number)) + port_number += 1 + """ Adding pins for Bank module""" for port in range(self.total_read): for bit in range(self.word_size): - self.add_pin("dout{0}[{1}]".format(port,bit),"OUT") + self.add_pin("dout{0}[{1}]".format(self.read_index[port],bit),"OUT") for port in range(self.total_write): for bit in range(self.word_size): self.add_pin("din{0}[{1}]".format(port,bit),"IN") @@ -84,7 +95,7 @@ class bank(design.design): for port in range(self.total_ports): self.add_pin("bank_sel{}".format(port),"INPUT") for port in range(self.total_read): - self.add_pin("s_en{0}".format(port), "INPUT") + self.add_pin("s_en{0}".format(self.read_index[port]), "INPUT") for port in range(self.total_write): self.add_pin("w_en{0}".format(port), "INPUT") for pin in ["clk_buf_bar","clk_buf"]: @@ -195,7 +206,7 @@ class bank(design.design): def add_modules(self): """ Create all the modules using the class loader """ - mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver", + mod_list = ["bitcell", "decoder", "wordline_driver", "bitcell_array", "sense_amp_array", "precharge_array", "column_mux_array", "write_driver_array", "dff", "bank_select"] @@ -232,9 +243,13 @@ class bank(design.design): self.add_mod(self.precharge_array[port]) if self.col_addr_size > 0: - self.column_mux_array = self.mod_column_mux_array(columns=self.num_cols, - word_size=self.word_size) - self.add_mod(self.column_mux_array) + self.column_mux_array = [] + for port in range(self.total_ports): + self.column_mux_array.append(self.mod_column_mux_array(columns=self.num_cols, + word_size=self.word_size, + bitcell_bl=self.read_bl_list[port], + bitcell_br=self.read_br_list[port])) + self.add_mod(self.column_mux_array[port]) self.sense_amp_array = self.mod_sense_amp_array(word_size=self.word_size, @@ -314,7 +329,7 @@ class bank(design.design): self.col_mux_array_inst = [] for port in range(self.total_ports): self.col_mux_array_inst.append(self.add_inst(name="column_mux_array{}".format(port), - mod=self.column_mux_array)) + mod=self.column_mux_array[port])) temp = [] for col in range(self.num_cols): @@ -331,7 +346,7 @@ class bank(design.design): def place_column_mux_array(self): """ Placing Column Mux when words_per_row > 1 . """ if self.col_addr_size > 0: - self.column_mux_height = self.column_mux_array.height + self.m2_gap + self.column_mux_height = self.column_mux_array[0].height + self.m2_gap else: self.column_mux_height = 0 return @@ -350,7 +365,7 @@ class bank(design.design): temp = [] for bit in range(self.word_size): - temp.append("dout{0}[{1}]".format(port,bit)) + temp.append("dout{0}[{1}]".format(self.read_index[port],bit)) if self.words_per_row == 1: temp.append(self.read_bl_list[port]+"[{0}]".format(bit)) temp.append(self.read_br_list[port]+"[{0}]".format(bit)) @@ -547,29 +562,35 @@ class bank(design.design): # These are the instances that every bank has top_instances = [self.bitcell_array_inst] - + for port in range(self.total_read): + #top_instances.append(self.precharge_array_inst[port]) + top_instances.append(self.sense_amp_array_inst[port]) + for port in range(self.total_write): + top_instances.append(self.write_driver_array_inst[port]) for port in range(self.total_ports): - top_instances.extend([self.precharge_array_inst[port], - self.sense_amp_array_inst[port], - self.write_driver_array_inst[port], - self.row_decoder_inst[port], + top_instances.extend([self.row_decoder_inst[port], self.wordline_driver_inst[port]]) # Add these if we use the part... if self.col_addr_size > 0: top_instances.append(self.col_decoder_inst[port]) - top_instances.append(self.col_mux_array_inst[port]) + #top_instances.append(self.col_mux_array_inst[port]) if self.num_banks > 1: top_instances.append(self.bank_select_inst[port]) - + + if self.col_addr_size > 0: + for port in range(self.total_ports): + self.copy_layout_pin(self.col_mux_array_inst[port], "gnd") + for port in range(self.total_read): + self.copy_layout_pin(self.precharge_array_inst[port], "vdd") for inst in top_instances: # Column mux has no vdd - if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst[0]): - self.copy_layout_pin(inst, "vdd") + #if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst[0]): + self.copy_layout_pin(inst, "vdd") # Precharge has no gnd - if inst != self.precharge_array_inst[0]: - self.copy_layout_pin(inst, "gnd") + #if inst != self.precharge_array_inst[port]: + self.copy_layout_pin(inst, "gnd") def route_bank_select(self): """ Route the bank select logic. """ diff --git a/compiler/modules/bitcell.py b/compiler/modules/bitcell.py index 38fd8823..4e741e24 100644 --- a/compiler/modules/bitcell.py +++ b/compiler/modules/bitcell.py @@ -50,16 +50,6 @@ class bitcell(design.design): row_pins = ["wl"] return row_pins - def list_read_wl_names(self): - """ Creates a list of wordline pin names associated with read ports """ - row_pins = ["wl"] - return row_pins - - def list_write_wl_names(self): - """ Creates a list of wordline pin names associated with write ports """ - row_pins = ["wl"] - return row_pins - def list_all_bitline_names(self): """ Creates a list of all bitline pin names (both bl and br) """ column_pins = ["bl", "br"] diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 02504313..78223d5f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -96,7 +96,7 @@ class control_logic(design.design): """ Setup bus names, determine the size of the busses etc """ # List of input control signals - self.input_list =["csb","web"] + self.input_list =["csb","web0"] self.dff_output_list =["cs_bar", "cs", "we_bar", "we"] # list of output control signals (for making a vertical bus) self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"] @@ -267,7 +267,7 @@ class control_logic(design.design): # Connect the clock rail to the other clock rail in_pos = self.ctrl_dff_inst.get_pin("clk").uc() - mid_pos = in_pos + vector(0,self.m2_pitch) + mid_pos = in_pos + vector(0,2*self.m2_pitch) rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos]) self.add_via_center(layers=("metal1","via1","metal2"), @@ -275,7 +275,7 @@ class control_logic(design.design): rotate=90) self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb") - self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web") + self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web0") def create_dffs(self): diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 62e424cb..d72aae2e 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -21,6 +21,25 @@ class dff(design.design): self.height = dff.height self.pin_map = dff.pin_map + def analytical_power(self, proc, vdd, temp, load): + """Returns dynamic and leakage power. Results in nW""" + from tech import spice + c_eff = self.calculate_effective_capacitance(load) + f = spice["default_event_rate"] + power_dyn = c_eff*vdd*vdd*f + power_leak = spice["msflop_leakage"] + + total_power = self.return_power(power_dyn, power_leak) + return total_power + + def calculate_effective_capacitance(self, load): + """Computes effective capacitance. Results in fF""" + from tech import spice, parameter + c_load = load + c_para = spice["flop_para_cap"]#ff + transition_prob = spice["flop_transition_prob"] + return transition_prob*(c_load + c_para) + def analytical_delay(self, slew, load = 0.0): # dont know how to calculate this now, use constant in tech file from tech import spice diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index d0699cc3..cec3a925 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -56,8 +56,8 @@ class hierarchical_predecode(design.design): # x offset for input inverters self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch - # x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch - self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 1) * self.m2_pitch + # x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches + self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch # x offset to output inverters self.x_off_inv_2 = self.x_off_nand + self.nand.width @@ -78,7 +78,7 @@ class hierarchical_predecode(design.design): invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)] non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)] decode_names = invert_names + non_invert_names - offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, 2*self.m1_width) + offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width) self.decode_rails = self.create_vertical_bus(layer="metal2", pitch=self.m2_pitch, offset=offset, diff --git a/compiler/modules/ms_flop.py b/compiler/modules/ms_flop.py deleted file mode 100644 index e04b4246..00000000 --- a/compiler/modules/ms_flop.py +++ /dev/null @@ -1,50 +0,0 @@ -import globals -import design -from math import log -import design -from tech import GDS,layer -import utils - -class ms_flop(design.design): - """ - Memory address flip-flop - """ - - pin_names = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"] - (width,height) = utils.get_libcell_size("ms_flop", GDS["unit"], layer["boundary"]) - pin_map = utils.get_libcell_pins(pin_names, "ms_flop", GDS["unit"], layer["boundary"]) - - def __init__(self, name="ms_flop"): - design.design.__init__(self, name) - - self.width = ms_flop.width - self.height = ms_flop.height - self.pin_map = ms_flop.pin_map - - def analytical_delay(self, slew, load = 0.0): - # dont know how to calculate this now, use constant in tech file - from tech import spice - result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"]) - return result - - def analytical_power(self, proc, vdd, temp, load): - """Returns dynamic and leakage power. Results in nW""" - from tech import spice - c_eff = self.calculate_effective_capacitance(load) - f = spice["default_event_rate"] - power_dyn = c_eff*vdd*vdd*f - power_leak = spice["msflop_leakage"] - - total_power = self.return_power(power_dyn, power_leak) - return total_power - - def calculate_effective_capacitance(self, load): - """Computes effective capacitance. Results in fF""" - from tech import spice, parameter - c_load = load - c_para = spice["flop_para_cap"]#ff - transistion_prob = spice["flop_transisition_prob"] - return transistion_prob*(c_load + c_para) - - - \ No newline at end of file diff --git a/compiler/modules/ms_flop_array.py b/compiler/modules/ms_flop_array.py deleted file mode 100644 index 061ad9be..00000000 --- a/compiler/modules/ms_flop_array.py +++ /dev/null @@ -1,136 +0,0 @@ -import debug -import design -from tech import drc -from math import log -from vector import vector -from globals import OPTS - -class ms_flop_array(design.design): - """ - An Array of D-Flipflops used for to store Data_in & Data_out of - Write_driver & Sense_amp, address inputs of column_mux & - hierdecoder - """ - - def __init__(self, columns, word_size, name=""): - self.columns = columns - self.word_size = word_size - if name=="": - name = "flop_array_c{0}_w{1}".format(columns,word_size) - design.design.__init__(self, name) - debug.info(1, "Creating {}".format(self.name)) - - self.words_per_row = int(self.columns / self.word_size) - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def create_netlist(self): - self.add_modules() - self.add_pins() - self.create_ms_flop_array() - - def create_layout(self): - self.width = self.columns * self.ms.width - self.height = self.ms.height - - self.place_ms_flop_array() - self.add_layout_pins() - self.DRC_LVS() - - def add_modules(self): - from importlib import reload - c = reload(__import__(OPTS.ms_flop)) - self.mod_ms_flop = getattr(c, OPTS.ms_flop) - self.ms = self.mod_ms_flop("ms_flop") - self.add_mod(self.ms) - - def add_pins(self): - for i in range(self.word_size): - self.add_pin("din[{0}]".format(i)) - for i in range(self.word_size): - self.add_pin("dout[{0}]".format(i)) - self.add_pin("dout_bar[{0}]".format(i)) - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") - - def create_ms_flop_array(self): - self.ms_inst={} - for i in range(0,self.columns,self.words_per_row): - name = "Xdff{0}".format(i) - index = int(i/self.words_per_row) - self.ms_inst[index]=self.add_inst(name=name, - mod=self.ms) - self.connect_inst(["din[{0}]".format(index), - "dout[{0}]".format(index), - "dout_bar[{0}]".format(index), - "clk", - "vdd", "gnd"]) - - def place_ms_flop_array(self): - for i in range(0,self.columns,self.words_per_row): - index = int(i/self.words_per_row) - if (i % 2 == 0 or self.words_per_row>1): - base = vector(i*self.ms.width,0) - mirror = "R0" - else: - base = vector((i+1)*self.ms.width,0) - mirror = "MY" - self.ms_inst[index].place(offset=base, - mirror=mirror) - - def add_layout_pins(self): - - for i in range(self.word_size): - - # Route both supplies - for n in ["vdd", "gnd"]: - for supply_pin in self.ms_inst[i].get_pins(n): - pin_pos = supply_pin.center() - self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=pin_pos) - self.add_layout_pin_rect_center(text=n, - layer="metal3", - offset=pin_pos) - - - din_pins = self.ms_inst[i].get_pins("din") - for din_pin in din_pins: - self.add_layout_pin(text="din[{}]".format(i), - layer=din_pin.layer, - offset=din_pin.ll(), - width=din_pin.width(), - height=din_pin.height()) - - dout_pin = self.ms_inst[i].get_pin("dout") - self.add_layout_pin(text="dout[{}]".format(i), - layer="metal2", - offset=dout_pin.ll(), - width=dout_pin.width(), - height=dout_pin.height()) - - doutbar_pin = self.ms_inst[i].get_pin("dout_bar") - self.add_layout_pin(text="dout_bar[{}]".format(i), - layer="metal2", - offset=doutbar_pin.ll(), - width=doutbar_pin.width(), - height=doutbar_pin.height()) - - - # Continous clk rail along with label. - self.add_layout_pin(text="clk", - layer="metal1", - offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1), - width=self.width, - height=drc["minwidth_metal1"]) - - - - - - - def analytical_delay(self, slew, load=0.0): - return self.ms.analytical_delay(slew=slew, load=load) - diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index 3a63c890..e23fa6aa 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -23,7 +23,7 @@ class multibank(design.design): def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""): - mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver", + mod_list = ["tri_gate", "bitcell", "decoder", "wordline_driver", "bitcell_array", "sense_amp_array", "precharge_array", "column_mux_array", "write_driver_array", "tri_gate_array", "dff", "bank_select"] diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index 6ca4a829..53430ac6 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -128,7 +128,22 @@ class replica_bitline(design.design): self.rbl_inst=self.add_inst(name="load", mod=self.rbl) - self.connect_inst(["bl[0]", "br[0]"] + ["gnd"]*self.bitcell_loads + ["vdd", "gnd"]) + + total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + temp = [] + temp.append("bl[0]") + temp.append("br[0]") + for port in range(total_ports - 1): + temp.append("gnd") + temp.append("gnd") + for wl in range(self.bitcell_loads): + for port in range(total_ports): + temp.append("gnd") + temp.append("vdd") + temp.append("gnd") + self.connect_inst(temp) + + self.wl_list = self.rbl.cell.list_all_wl_names() def place_modules(self): """ Add all of the module instances in the logical netlist """ @@ -160,7 +175,7 @@ class replica_bitline(design.design): """ Connect the RBL word lines to gnd """ # Connect the WL and gnd pins directly to the center and right gnd rails for row in range(self.bitcell_loads): - wl = "wl[{}]".format(row) + wl = self.wl_list[0]+"[{}]".format(row) pin = self.rbl_inst.get_pin(wl) # Route the connection to the right so that it doesn't interfere @@ -371,7 +386,7 @@ class replica_bitline(design.design): # Connect the WL and gnd pins directly to the center and right gnd rails for row in range(self.bitcell_loads): - wl = "wl[{}]".format(row) + wl = self.wl_list[0]+"[{}]".format(row) pin = self.rbl_inst.get_pin(wl) if pin.layer != "metal1": continue diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index d9be378f..e7ef1166 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -14,12 +14,18 @@ class single_level_column_mux_array(design.design): Array of column mux to read the bitlines through the 6T. """ - def __init__(self, columns, word_size): - design.design.__init__(self, "columnmux_array") + unique_id = 1 + + def __init__(self, columns, word_size, bitcell_bl="bl", bitcell_br="br"): + name="single_level_column_mux_array_{}".format(single_level_column_mux_array.unique_id) + single_level_column_mux_array.unique_id += 1 + design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.columns = columns self.word_size = word_size self.words_per_row = int(self.columns / self.word_size) + self.bitcell_bl = bitcell_bl + self.bitcell_br = bitcell_br self.create_netlist() if not OPTS.netlist_only: @@ -56,7 +62,7 @@ class single_level_column_mux_array(design.design): def add_modules(self): # FIXME: Why is this 8x? - self.mux = single_level_column_mux(tx_size=8) + self.mux = single_level_column_mux(tx_size=8, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) self.add_mod(self.mux) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 3deac4e1..277e8003 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -52,10 +52,6 @@ class wordline_driver(design.design): def add_modules(self): # This is just used for measurements, # so don't add the module - from importlib import reload - c = reload(__import__(OPTS.bitcell)) - self.mod_bitcell = getattr(c, OPTS.bitcell) - self.bitcell = self.mod_bitcell() self.inv = pinv() self.add_mod(self.inv) @@ -134,12 +130,8 @@ class wordline_driver(design.design): inv2_xoffset = nand2_xoffset + self.nand2.width self.width = inv2_xoffset + self.inv.height - if self.bitcell.height > self.inv.height: - self.height = self.bitcell.height * self.rows - driver_height = self.bitcell.height - else: - self.height = self.inv.height * self.rows - driver_height = self.inv.height + driver_height = self.inv.height + self.height = self.inv.height * self.rows for row in range(self.rows): if (row % 2): diff --git a/compiler/options.py b/compiler/options.py index 5298c00f..58d97ea0 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -50,6 +50,8 @@ class options(optparse.Values): analytical_delay = True # Purge the temp directory after a successful run (doesn't purge on errors, anyhow) purge_temp = True + # Determines whether multi-port portion of unit tests are run or not + multiport_check = True # These are the configuration parameters num_rw_ports = 1 @@ -69,8 +71,7 @@ class options(optparse.Values): # These are the default modules that can be over-riden decoder = "hierarchical_decoder" - ms_flop = "ms_flop" - ms_flop_array = "ms_flop_array" + dff_array = "dff_array" dff = "dff" control_logic = "control_logic" bitcell_array = "bitcell_array" diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py index 6f579c06..24fdfb60 100644 --- a/compiler/pgates/pbitcell.py +++ b/compiler/pgates/pbitcell.py @@ -17,6 +17,7 @@ class pbitcell(design.design): self.num_rw_ports = OPTS.num_rw_ports self.num_w_ports = OPTS.num_w_ports self.num_r_ports = OPTS.num_r_ports + self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports name = "pbitcell_{0}RW_{1}W_{2}R".format(self.num_rw_ports, self.num_w_ports, self.num_r_ports) # This is not a pgate because pgates depend on the bitcell height! @@ -53,38 +54,79 @@ class pbitcell(design.design): if(self.num_rw_ports > 0): self.place_readwrite_ports() + self.route_readwrite_wordlines() + self.route_readwrite_bitlines() + if(self.num_w_ports == 0): # routing for write to storage is the same as read/write to storage + self.route_readwrite_access() if(self.num_w_ports > 0): self.place_write_ports() + self.route_write_wordlines() + self.route_write_bitlines() + self.route_write_access() if(self.num_r_ports > 0): self.place_read_ports() + self.route_read_wordlines() + self.route_read_bitlines() + self.route_read_access() self.extend_well() self.offset_all_coordinates() self.DRC_LVS() def add_pins(self): + self.rw_bl_names = [] + self.rw_br_names = [] + self.w_bl_names = [] + self.w_br_names = [] + self.r_bl_names = [] + self.r_br_names = [] + self.rw_wl_names = [] + self.w_wl_names = [] + self.r_wl_names = [] + port = 0 + for k in range(self.num_rw_ports): - self.add_pin("rwbl{}".format(k)) - self.add_pin("rwbl_bar{}".format(k)) + self.add_pin("bl{}".format(port)) + self.add_pin("br{}".format(port)) + self.rw_bl_names.append("bl{}".format(port)) + self.rw_br_names.append("br{}".format(port)) + port += 1 for k in range(self.num_w_ports): - self.add_pin("wbl{}".format(k)) - self.add_pin("wbl_bar{}".format(k)) + self.add_pin("bl{}".format(port)) + self.add_pin("br{}".format(port)) + self.w_bl_names.append("bl{}".format(port)) + self.w_br_names.append("br{}".format(port)) + port += 1 for k in range(self.num_r_ports): - self.add_pin("rbl{}".format(k)) - self.add_pin("rbl_bar{}".format(k)) + self.add_pin("bl{}".format(port)) + self.add_pin("br{}".format(port)) + self.r_bl_names.append("bl{}".format(port)) + self.r_br_names.append("br{}".format(port)) + port += 1 + port = 0 for k in range(self.num_rw_ports): - self.add_pin("rwwl{}".format(k)) + self.add_pin("wl{}".format(port)) + self.rw_wl_names.append("wl{}".format(port)) + port += 1 for k in range(self.num_w_ports): - self.add_pin("wwl{}".format(k)) + self.add_pin("wl{}".format(port)) + self.w_wl_names.append("wl{}".format(port)) + port += 1 for k in range(self.num_r_ports): - self.add_pin("rwl{}".format(k)) + self.add_pin("wl{}".format(port)) + self.r_wl_names.append("wl{}".format(port)) + port += 1 self.add_pin("vdd") self.add_pin("gnd") + def add_modules(self): - # if there are any read/write ports, then the inverter nmos is sized based the number of them + """ + Determine size of transistors and add ptx modules + """ + # if there are any read/write ports, then the inverter nmos is sized based the number of read/write ports if(self.num_rw_ports > 0): inverter_nmos_width = self.num_rw_ports*3*parameter["min_tx_size"] inverter_pmos_width = parameter["min_tx_size"] @@ -92,7 +134,7 @@ class pbitcell(design.design): write_nmos_width = parameter["min_tx_size"] read_nmos_width = 2*parameter["min_tx_size"] - # if there are no read/write ports, then the inverter nmos is sized for the dual port case + # if there are no read/write ports, then the inverter nmos is statically sized for the dual port case else: inverter_nmos_width = 2*parameter["min_tx_size"] inverter_pmos_width = parameter["min_tx_size"] @@ -100,7 +142,6 @@ class pbitcell(design.design): write_nmos_width = parameter["min_tx_size"] read_nmos_width = 2*parameter["min_tx_size"] - """ Create ptx for all transistors """ # create ptx for inverter transistors self.inverter_nmos = ptx(width=inverter_nmos_width, tx_type="nmos") @@ -180,17 +221,17 @@ class pbitcell(design.design): self.write_to_read_spacing = write_portion + read_portion + 2*contact.poly.width + drc["poly_to_polycontact"] - """ calculations for transistor tiling (transistor + spacing) """ + # calculations for transistor tiling (transistor + spacing) self.inverter_tile_width = self.inverter_nmos.active_width + 0.5*self.inverter_to_inverter_spacing self.readwrite_tile_width = self.readwrite_to_readwrite_spacing + self.readwrite_nmos.active_height self.write_tile_width = self.write_to_write_spacing + self.write_nmos.active_height self.read_tile_width = self.read_to_read_spacing + self.read_nmos.active_height - """ calculation for row line tiling """ - self.rail_tile_height = drc["active_to_body_active"] + contact.well.width #0.5*(drc["minwidth_tx"] - drc["minwidth_metal1"]) + drc["minwidth_metal1"] + # calculation for row line tiling + self.rail_tile_height = drc["active_to_body_active"] + contact.well.width self.rowline_tile_height = drc["minwidth_metal1"] + contact.m1m2.width - """ calculations related to inverter connections """ + # calculations related to inverter connections self.inverter_gap = drc["poly_to_active"] + drc["poly_to_polycontact"] + 2*contact.poly.width + drc["minwidth_metal1"] + self.inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos.active_height + drc["poly_to_active"] + 0.5*contact.poly.width self.cross_couple_upper_ypos = self.inverter_nmos.active_height + drc["poly_to_active"] + drc["poly_to_polycontact"] + 1.5*contact.poly.width @@ -198,7 +239,7 @@ class pbitcell(design.design): def calculate_postions(self): """ - Calculate positions that describe the edges of the cell + Calculate positions that describe the edges and dimensions of the cell """ # create flags for excluding readwrite, write, or read port calculations if they are not included in the bitcell if(self.num_rw_ports > 0): @@ -286,8 +327,7 @@ class pbitcell(design.design): def place_storage(self): """ - Places the crossed coupled inverters that act as storage for the bitcell. - The stored value of the cell is denoted as "Q", and the inverted value as "Q_bar". + Places the transistors for the crossed coupled inverters in the bitcell """ # calculate transistor offsets @@ -304,7 +344,9 @@ class pbitcell(design.design): self.inverter_pmos_right.place([right_inverter_xpos, inverter_pmos_ypos]) def route_storage(self): - + """ + Routes inputs and outputs of inverters to cross couple them + """ # connect input (gate) of inverters self.add_path("poly", [self.inverter_nmos_left.get_pin("G").uc(), self.inverter_pmos_left.get_pin("G").bc()]) self.add_path("poly", [self.inverter_nmos_right.get_pin("G").uc(), self.inverter_pmos_right.get_pin("G").bc()]) @@ -338,9 +380,8 @@ class pbitcell(design.design): def route_rails(self): """ - Add gnd and vdd rails and connects them to the inverters + Adds gnd and vdd rails and connects them to the inverters """ - # Add rails for vdd and gnd self.gnd_position = vector(self.leftmost_xpos, -self.rail_tile_height) self.gnd = self.add_layout_pin(text="gnd", @@ -393,11 +434,11 @@ class pbitcell(design.design): # add read/write transistors self.readwrite_nmos_left[k] = self.add_inst(name="readwrite_nmos_left{}".format(k), mod=self.readwrite_nmos) - self.connect_inst(["Q", "rwwl{}".format(k), "rwbl{}".format(k), "gnd"]) + self.connect_inst(["Q", self.rw_wl_names[k], self.rw_bl_names[k], "gnd"]) self.readwrite_nmos_right[k] = self.add_inst(name="readwrite_nmos_right{}".format(k), mod=self.readwrite_nmos) - self.connect_inst(["Q_bar", "rwwl{}".format(k), "rwbl_bar{}".format(k), "gnd"]) + self.connect_inst(["Q_bar", self.rw_wl_names[k], self.rw_br_names[k], "gnd"]) def place_readwrite_ports(self): @@ -440,46 +481,43 @@ class pbitcell(design.design): self.rwwl_positions[k] = vector(self.leftmost_xpos, rwwl_ypos) # add pin for RWWL - self.add_layout_pin(text="rwwl{}".format(k), + self.add_layout_pin(text=self.rw_wl_names[k], layer="metal1", offset=self.rwwl_positions[k], width=self.width, height=contact.m1m2.width) - - # Source/RWBL/RWBL_bar connections - # add metal1-to-metal2 contacts on top of read/write transistor source pins for connection to WBL and WBL_bar - offset_left = self.readwrite_nmos_left[k].get_pin("S").center() - self.add_contact_center(layers=("metal1", "via1", "metal2"), - offset=offset_left, - rotate=90) - - offset_right = self.readwrite_nmos_right[k].get_pin("S").center() - self.add_contact_center(layers=("metal1", "via1", "metal2"), - offset=offset_right, - rotate=90) - + # add pins for RWBL and RWBL_bar, overlaid on source contacts self.rwbl_positions[k] = vector(self.readwrite_nmos_left[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos) - self.add_layout_pin(text="rwbl{}".format(k), + self.add_layout_pin(text=self.rw_bl_names[k], layer="metal2", offset=self.rwbl_positions[k], width=drc["minwidth_metal2"], height=self.height) self.rwbl_bar_positions[k] = vector(self.readwrite_nmos_right[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos) - self.add_layout_pin(text="rwbl_bar{}".format(k), + self.add_layout_pin(text=self.rw_br_names[k], layer="metal2", offset=self.rwbl_bar_positions[k], width=drc["minwidth_metal2"], height=self.height) - + + # update furthest left and right transistor edges + self.left_building_edge = left_readwrite_transistor_xpos - self.readwrite_nmos.active_height + self.right_building_edge = right_readwrite_transistor_xpos + + def route_readwrite_wordlines(self): + """ + Routes read/write trnasistors to their respective wordlines + """ + for k in range(0,self.num_rw_ports): # Gate/RWWL connections # add poly-to-meltal2 contacts to connect gate of read/write transistors to RWWL (contact next to gate) # contact must be placed a metal1 width below the source pin to avoid drc from source pin routings if(self.readwrite_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.readwrite_nmos_left[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width else: - contact_xpos = left_readwrite_transistor_xpos - self.readwrite_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width + contact_xpos = self.readwrite_nmos_left[k].offset.x - self.readwrite_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width contact_ypos = self.readwrite_nmos_left[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height left_gate_contact = vector(contact_xpos, contact_ypos) @@ -491,7 +529,7 @@ class pbitcell(design.design): if(self.readwrite_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.readwrite_nmos_right[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width else: - contact_xpos = right_readwrite_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width + contact_xpos = self.readwrite_nmos_right[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width contact_ypos = self.readwrite_nmos_right[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height right_gate_contact = vector(contact_xpos, contact_ypos) @@ -521,45 +559,62 @@ class pbitcell(design.design): # connect read/write transistor gate contacts to RWWL contacts (metal2 path) self.add_path("metal2", [left_gate_contact, left_rwwl_contact]) self.add_path("metal2", [right_gate_contact, right_rwwl_contact]) - - # Drain/Storage connections - # this path only needs to be drawn once on the last iteration of the loop - if(k == self.num_rw_ports-1): - # add contacts to connect gate of inverters to drain of read/write transistors - left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos) - self.add_contact_center(layers=("poly", "contact", "metal1"), - offset=left_storage_contact, - rotate=90) - - right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos) - self.add_contact_center(layers=("poly", "contact", "metal1"), - offset=right_storage_contact, - rotate=90) - - # connect gate of inverters to contacts (poly path) - inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos) - self.add_path("poly", [left_storage_contact, inverter_gate_offset_left]) - - inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos) - self.add_path("poly", [right_storage_contact, inverter_gate_offset_right]) - - # connect contacts to drains of read/write transistors (metal1 path) - midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y) - midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.readwrite_nmos_left[k].get_pin("D").lc().y) - self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error - self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.readwrite_nmos_left[k].get_pin("D").lc()]) - - midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y) - midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.readwrite_nmos_right[k].get_pin("D").rc().y) - self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width) - self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.readwrite_nmos_right[k].get_pin("D").rc()]) - # end if - # end for - # update furthest left and right transistor edges - self.left_building_edge = left_readwrite_transistor_xpos - self.readwrite_nmos.active_height - self.right_building_edge = right_readwrite_transistor_xpos + def route_readwrite_bitlines(self): + """ + Routes read/write transistors to their respective bitlines + """ + for k in range(0,self.num_rw_ports): + # Source/RWBL/RWBL_bar connections + # add metal1-to-metal2 contacts on top of read/write transistor source pins for connection to WBL and WBL_bar + offset_left = self.readwrite_nmos_left[k].get_pin("S").center() + self.add_contact_center(layers=("metal1", "via1", "metal2"), + offset=offset_left, + rotate=90) + + offset_right = self.readwrite_nmos_right[k].get_pin("S").center() + self.add_contact_center(layers=("metal1", "via1", "metal2"), + offset=offset_right, + rotate=90) + + + def route_readwrite_access(self): + """ + Routes read/write transistors to the storage component of the bitcell + """ + last_inst = self.num_rw_ports - 1 + + # Drain/Storage connections + # this path only needs to be drawn once on the last iteration of the loop + # add contacts to connect gate of inverters to drain of read/write transistors + left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos) + self.add_contact_center(layers=("poly", "contact", "metal1"), + offset=left_storage_contact, + rotate=90) + + right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos) + self.add_contact_center(layers=("poly", "contact", "metal1"), + offset=right_storage_contact, + rotate=90) + + # connect gate of inverters to contacts (poly path) + inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos) + self.add_path("poly", [left_storage_contact, inverter_gate_offset_left]) + + inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos) + self.add_path("poly", [right_storage_contact, inverter_gate_offset_right]) + + # connect contacts to drains of read/write transistors (metal1 path) + midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y) + midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.readwrite_nmos_left[last_inst].get_pin("D").lc().y) + self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error + self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.readwrite_nmos_left[last_inst].get_pin("D").lc()]) + + midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y) + midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.readwrite_nmos_right[last_inst].get_pin("D").rc().y) + self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width) + self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.readwrite_nmos_right[last_inst].get_pin("D").rc()]) def create_write_ports(self): """ @@ -583,18 +638,17 @@ class pbitcell(design.design): # add write transistors self.write_nmos_left[k] = self.add_inst(name="write_nmos_left{}".format(k), mod=self.write_nmos) - self.connect_inst(["Q", "wwl{}".format(k), "wbl{}".format(k), "gnd"]) + self.connect_inst(["Q", self.w_wl_names[k], self.w_bl_names[k], "gnd"]) self.write_nmos_right[k] = self.add_inst(name="write_nmos_right{}".format(k), mod=self.write_nmos) - self.connect_inst(["Q_bar", "wwl{}".format(k), "wbl_bar{}".format(k), "gnd"]) + self.connect_inst(["Q_bar", self.w_wl_names[k], self.w_br_names[k], "gnd"]) def place_write_ports(self): """ Places write ports in the bit cell. """ - # Define variables relevant to write transistors self.wwl_positions = [None] * self.num_w_ports self.wbl_positions = [None] * self.num_w_ports @@ -634,46 +688,43 @@ class pbitcell(design.design): self.wwl_positions[k] = vector(self.leftmost_xpos, wwl_ypos) # add pin for WWL - self.add_layout_pin(text="wwl{}".format(k), + self.add_layout_pin(text=self.w_wl_names[k], layer="metal1", offset=self.wwl_positions[k], width=self.width, height=contact.m1m2.width) - # Source/WBL/WBL_bar connections - # add metal1-to-metal2 contacts on top of write transistor source pins for connection to WBL and WBL_bar - offset_left = self.write_nmos_left[k].get_pin("S").center() - self.add_contact_center(layers=("metal1", "via1", "metal2"), - offset=offset_left, - rotate=90) - - offset_right = self.write_nmos_right[k].get_pin("S").center() - self.add_contact_center(layers=("metal1", "via1", "metal2"), - offset=offset_right, - rotate=90) - # add pins for WBL and WBL_bar, overlaid on source contacts self.wbl_positions[k] = vector(self.write_nmos_left[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos) - self.add_layout_pin(text="wbl{}".format(k), + self.add_layout_pin(text=self.w_bl_names[k], layer="metal2", offset=self.wbl_positions[k], width=drc["minwidth_metal2"], height=self.height) self.wbl_bar_positions[k] = vector(self.write_nmos_right[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos) - self.add_layout_pin(text="wbl_bar{}".format(k), + self.add_layout_pin(text=self.w_br_names[k], layer="metal2", offset=self.wbl_bar_positions[k], width=drc["minwidth_metal2"], height=self.height) - + + # update furthest left and right transistor edges + self.left_building_edge = left_write_transistor_xpos - self.write_nmos.active_height + self.right_building_edge = right_write_transistor_xpos + + def route_write_wordlines(self): + """ + Routes write transistors to their respective wordlines + """ + for k in range(0,self.num_w_ports): # Gate/WWL connections # add poly-to-meltal2 contacts to connect gate of write transistors to WWL (contact next to gate) # contact must be placed a metal width below the source pin to avoid drc from source pin routings if(self.write_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.write_nmos_left[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width else: - contact_xpos = left_write_transistor_xpos - self.write_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width + contact_xpos = self.write_nmos_left[k].offset.x - self.write_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width contact_ypos = self.write_nmos_left[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height left_gate_contact = vector(contact_xpos, contact_ypos) @@ -685,7 +736,7 @@ class pbitcell(design.design): if(self.write_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.write_nmos_right[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width else: - contact_xpos = right_write_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width + contact_xpos = self.write_nmos_right[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width contact_ypos = self.write_nmos_right[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height right_gate_contact = vector(contact_xpos, contact_ypos) @@ -715,42 +766,60 @@ class pbitcell(design.design): # connect write transistor gate contacts to WWL contacts (metal2 path) self.add_path("metal2", [left_gate_contact, left_wwl_contact]) self.add_path("metal2", [right_gate_contact, right_wwl_contact]) - - # Drain/Storage connections - # this path only needs to be drawn once on the last iteration of the loop - if(k == self.num_w_ports-1): - # add contacts to connect gate of inverters to drain of write transistors - left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos) - self.add_contact_center(layers=("poly", "contact", "metal1"), - offset=left_storage_contact, - rotate=90) + + def route_write_bitlines(self): + """ + Routes write transistors to their respective bitlines + """ + for k in range(0,self.num_w_ports): + # Source/WBL/WBL_bar connections + # add metal1-to-metal2 contacts on top of write transistor source pins for connection to WBL and WBL_bar + offset_left = self.write_nmos_left[k].get_pin("S").center() + self.add_contact_center(layers=("metal1", "via1", "metal2"), + offset=offset_left, + rotate=90) + + offset_right = self.write_nmos_right[k].get_pin("S").center() + self.add_contact_center(layers=("metal1", "via1", "metal2"), + offset=offset_right, + rotate=90) - right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos) - self.add_contact_center(layers=("poly", "contact", "metal1"), - offset=right_storage_contact, - rotate=90) - - # connect gate of inverters to contacts (poly path) - inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos) - self.add_path("poly", [left_storage_contact, inverter_gate_offset_left]) - - inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos) - self.add_path("poly", [right_storage_contact, inverter_gate_offset_right]) - - # connect contacts to drains of write transistors (metal1 path) - midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y) - midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.write_nmos_left[k].get_pin("D").lc().y) - self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error - self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.write_nmos_left[k].get_pin("D").lc()]) - - midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y) - midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.write_nmos_right[k].get_pin("D").rc().y) - self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width) - self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.write_nmos_right[k].get_pin("D").rc()]) + def route_write_access(self): + """ + Routes write transistors to the storage component of the bitcell + """ + last_inst = self.num_w_ports - 1 + + # Drain/Storage connections + # this path only needs to be drawn once on the last iteration of the loop + # add contacts to connect gate of inverters to drain of write transistors + left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos) + self.add_contact_center(layers=("poly", "contact", "metal1"), + offset=left_storage_contact, + rotate=90) - # update furthest left and right transistor edges - self.left_building_edge = left_write_transistor_xpos - self.write_nmos.active_height - self.right_building_edge = right_write_transistor_xpos + right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos) + self.add_contact_center(layers=("poly", "contact", "metal1"), + offset=right_storage_contact, + rotate=90) + + # connect gate of inverters to contacts (poly path) + inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos) + self.add_path("poly", [left_storage_contact, inverter_gate_offset_left]) + + inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos) + self.add_path("poly", [right_storage_contact, inverter_gate_offset_right]) + + # connect contacts to drains of write transistors (metal1 path) + midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y) + midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.write_nmos_left[last_inst].get_pin("D").lc().y) + self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error + self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.write_nmos_left[last_inst].get_pin("D").lc()]) + + midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y) + midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.write_nmos_right[last_inst].get_pin("D").rc().y) + self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width) + self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.write_nmos_right[last_inst].get_pin("D").rc()]) def create_read_ports(self): @@ -785,17 +854,16 @@ class pbitcell(design.design): # add read transistors self.read_nmos_left[k] = self.add_inst(name="read_nmos_left{}".format(k), mod=self.read_nmos) - self.connect_inst(["rbl{}".format(k), "rwl{}".format(k), "RA_to_R_left{}".format(k), "gnd"]) + self.connect_inst([self.r_bl_names[k], self.r_wl_names[k], "RA_to_R_left{}".format(k), "gnd"]) self.read_nmos_right[k] = self.add_inst(name="read_nmos_right{}".format(k), mod=self.read_nmos) - self.connect_inst(["rbl_bar{}".format(k), "rwl{}".format(k), "RA_to_R_right{}".format(k), "gnd"]) + self.connect_inst([self.r_br_names[k], self.r_wl_names[k], "RA_to_R_right{}".format(k), "gnd"]) def place_read_ports(self): """ Places the read ports in the bit cell. """ - # Define variables relevant to read transistors self.rwl_positions = [None] * self.num_r_ports self.rbl_positions = [None] * self.num_r_ports @@ -844,45 +912,38 @@ class pbitcell(design.design): self.rwl_positions[k] = vector(self.leftmost_xpos, rwl_ypos) # add pin for RWL - self.add_layout_pin(text="rwl{}".format(k), + self.add_layout_pin(text=self.r_wl_names[k], layer="metal1", offset=self.rwl_positions[k], width=self.width, height=contact.m1m2.width) - - # Drain of read transistor / RBL & RBL_bar connection - # add metal1-to-metal2 contacts on top of read transistor drain pins for connection to RBL and RBL_bar - offset_left = self.read_nmos_left[k].get_pin("D").center() - self.add_contact_center(layers=("metal1", "via1", "metal2"), - offset=offset_left, - rotate=90) - - offset_right = self.read_nmos_right[k].get_pin("D").center() - self.add_contact_center(layers=("metal1", "via1", "metal2"), - offset=offset_right, - rotate=90) # add pins for RBL and RBL_bar, overlaid on drain contacts self.rbl_positions[k] = vector(self.read_nmos_left[k].get_pin("D").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos) - self.add_layout_pin(text="rbl{}".format(k), + self.add_layout_pin(text=self.r_bl_names[k], layer="metal2", offset=self.rbl_positions[k], width=drc["minwidth_metal2"], height=self.height) self.rbl_bar_positions[k] = vector(self.read_nmos_right[k].get_pin("D").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos) - self.add_layout_pin(text="rbl_bar{}".format(k), + self.add_layout_pin(text=self.r_br_names[k], layer="metal2", offset=self.rbl_bar_positions[k], width=drc["minwidth_metal2"], height=self.height) - + + def route_read_wordlines(self): + """ + Routes read transistors to their respective worlines + """ + for k in range(0,self.num_r_ports): # Gate of read transistor / RWL connection # add poly-to-meltal2 contacts to connect gate of read transistors to RWL (contact next to gate) if(self.read_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.read_nmos_left[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width else: - contact_xpos = left_read_transistor_xpos - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width + contact_xpos = self.read_nmos_left[k].offset.x - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width contact_ypos = self.read_nmos_left[k].get_pin("G").lc().y left_gate_contact = vector(contact_xpos, contact_ypos) @@ -894,7 +955,7 @@ class pbitcell(design.design): if(self.read_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.read_nmos_right[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width else: - contact_xpos = right_read_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width + contact_xpos = self.read_nmos_right[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width contact_ypos = self.read_nmos_right[k].get_pin("G").rc().y right_gate_contact = vector(contact_xpos, contact_ypos) @@ -929,13 +990,35 @@ class pbitcell(design.design): gnd_offset_right = vector(self.read_access_nmos_right[k].get_pin("S").bc().x, self.gnd_position.y) self.add_path("metal1", [self.read_access_nmos_right[k].get_pin("S").bc(), gnd_offset_right]) + + def route_read_bitlines(self): + """ + Routes read transistors to their respective bitlines + """ + for k in range(0,self.num_r_ports): + # Drain of read transistor / RBL & RBL_bar connection + # add metal1-to-metal2 contacts on top of read transistor drain pins for connection to RBL and RBL_bar + offset_left = self.read_nmos_left[k].get_pin("D").center() + self.add_contact_center(layers=("metal1", "via1", "metal2"), + offset=offset_left, + rotate=90) + offset_right = self.read_nmos_right[k].get_pin("D").center() + self.add_contact_center(layers=("metal1", "via1", "metal2"), + offset=offset_right, + rotate=90) + + def route_read_access(self): + """ + Routes read access transistors to the storage component of the bitcell + """ + for k in range(0,self.num_r_ports): # Gate of read-access transistor / storage connection # add poly-to-metal1 contacts to connect gate of read-access transistors to output of inverters (contact next to gate) if(self.read_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.read_nmos_left[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width else: - contact_xpos = left_read_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width + contact_xpos = self.read_nmos_left[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width contact_ypos = self.read_access_nmos_left[k].get_pin("G").rc().y left_gate_contact = vector(contact_xpos, contact_ypos) @@ -945,7 +1028,7 @@ class pbitcell(design.design): if(self.read_nmos_contact_extension > self.gate_contact_thres): contact_xpos = self.read_nmos_right[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width else: - contact_xpos = right_read_transistor_xpos - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width + contact_xpos = self.read_nmos_right[k].offset.x - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width contact_ypos = self.read_access_nmos_right[k].get_pin("G").lc().y right_gate_contact = vector(contact_xpos, contact_ypos) @@ -977,8 +1060,6 @@ class pbitcell(design.design): midR2 = vector(right_gate_contact0.x, self.cross_couple_upper_ypos) right_inverter_offset = vector(self.inverter_nmos_right.get_pin("S").center().x, self.cross_couple_upper_ypos) self.add_path("metal1", [right_gate_contact, midR0, midR1, midR2, right_inverter_offset]) - # end for - def extend_well(self): """ @@ -1083,134 +1164,54 @@ class pbitcell(design.design): def list_bitcell_pins(self, col, row): """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ bitcell_pins = [] - for k in range(self.num_rw_ports): - bitcell_pins.append("rwbl{0}[{1}]".format(k,col)) - bitcell_pins.append("rwbl_bar{0}[{1}]".format(k,col)) - for k in range(self.num_w_ports): - bitcell_pins.append("wbl{0}[{1}]".format(k,col)) - bitcell_pins.append("wbl_bar{0}[{1}]".format(k,col)) - for k in range(self.num_r_ports): - bitcell_pins.append("rbl{0}[{1}]".format(k,col)) - bitcell_pins.append("rbl_bar{0}[{1}]".format(k,col)) - for k in range(self.num_rw_ports): - bitcell_pins.append("rwwl{0}[{1}]".format(k,row)) - for k in range(self.num_w_ports): - bitcell_pins.append("wwl{0}[{1}]".format(k,row)) - for k in range(self.num_r_ports): - bitcell_pins.append("rwl{0}[{1}]".format(k,row)) + for port in range(self.total_ports): + bitcell_pins.append("bl{0}[{1}]".format(port,col)) + bitcell_pins.append("br{0}[{1}]".format(port,col)) + for port in range(self.total_ports): + bitcell_pins.append("wl{0}[{1}]".format(port,row)) bitcell_pins.append("vdd") bitcell_pins.append("gnd") - return bitcell_pins def list_all_wl_names(self): """ Creates a list of all wordline pin names """ - row_pins = [] - for k in range(self.num_rw_ports): - row_pins.append("rwwl{0}".format(k)) - for k in range(self.num_w_ports): - row_pins.append("wwl{0}".format(k)) - for k in range(self.num_r_ports): - row_pins.append("rwl{0}".format(k)) - - return row_pins - - def list_read_wl_names(self): - """ Creates a list of wordline pin names associated with read ports """ - row_pins = [] - for k in range(self.num_rw_ports): - row_pins.append("rwwl{0}".format(k)) - for k in range(self.num_r_ports): - row_pins.append("rwl{0}".format(k)) - - return row_pins - - def list_write_wl_names(self): - """ Creates a list of wordline pin names associated with write ports """ - row_pins = [] - for k in range(self.num_rw_ports): - row_pins.append("rwwl{0}".format(k)) - for k in range(self.num_w_ports): - row_pins.append("wwl{0}".format(k)) - - return row_pins - + wordline_names = self.rw_wl_names + self.w_wl_names + self.r_wl_names + return wordline_names def list_all_bitline_names(self): """ Creates a list of all bitline pin names (both bl and br) """ - column_pins = [] - for k in range(self.num_rw_ports): - column_pins.append("rwbl{0}".format(k)) - column_pins.append("rwbl_bar{0}".format(k)) - for k in range(self.num_w_ports): - column_pins.append("wbl{0}".format(k)) - column_pins.append("wbl_bar{0}".format(k)) - for k in range(self.num_r_ports): - column_pins.append("rbl{0}".format(k)) - column_pins.append("rbl_bar{0}".format(k)) - - return column_pins + bitline_pins = [] + for port in range(self.total_ports): + bitline_pins.append("bl{0}".format(port)) + bitline_pins.append("br{0}".format(port)) + return bitline_pins def list_all_bl_names(self): """ Creates a list of all bl pins names """ - column_pins = [] - for k in range(self.num_rw_ports): - column_pins.append("rwbl{0}".format(k)) - for k in range(self.num_w_ports): - column_pins.append("wbl{0}".format(k)) - for k in range(self.num_r_ports): - column_pins.append("rbl{0}".format(k)) - - return column_pins + bl_pins = self.rw_bl_names + self.w_bl_names + self.r_bl_names + return bl_pins def list_all_br_names(self): """ Creates a list of all br pins names """ - column_pins = [] - for k in range(self.num_rw_ports): - column_pins.append("rwbl_bar{0}".format(k)) - for k in range(self.num_w_ports): - column_pins.append("wbl_bar{0}".format(k)) - for k in range(self.num_r_ports): - column_pins.append("rbl_bar{0}".format(k)) - - return column_pins + br_pins = self.rw_br_names + self.w_br_names + self.r_br_names + return br_pins def list_read_bl_names(self): """ Creates a list of bl pin names associated with read ports """ - column_pins = [] - for k in range(self.num_rw_ports): - column_pins.append("rwbl{0}".format(k)) - for k in range(self.num_r_ports): - column_pins.append("rbl{0}".format(k)) - - return column_pins + bl_pins = self.rw_bl_names + self.r_bl_names + return bl_pins def list_read_br_names(self): """ Creates a list of br pin names associated with read ports """ - column_pins = [] - for k in range(self.num_rw_ports): - column_pins.append("rwbl_bar{0}".format(k)) - for k in range(self.num_r_ports): - column_pins.append("rbl_bar{0}".format(k)) - - return column_pins + br_pins = self.rw_br_names + self.r_br_names + return br_pins def list_write_bl_names(self): """ Creates a list of bl pin names associated with write ports """ - column_pins = [] - for k in range(self.num_rw_ports): - column_pins.append("rwbl{0}".format(k)) - for k in range(self.num_w_ports): - column_pins.append("wbl{0}".format(k)) - - return column_pins + bl_pins = self.rw_bl_names + self.w_bl_names + return bl_pins def list_write_br_names(self): """ Creates a list of br pin names asscociated with write ports""" - column_pins = [] - for k in range(self.num_rw_ports): - column_pins.append("rwbl_bar{0}".format(k)) - for k in range(self.num_w_ports): - column_pins.append("wbl_bar{0}".format(k)) - - return column_pins + br_pins = self.rw_br_names + self.w_br_names + return br_pins diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index e39f95bc..8b3d1716 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -279,5 +279,5 @@ class pinv(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["inv_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["inv_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index d38c7de4..14923a84 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -240,5 +240,5 @@ class pnand2(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["nand2_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["nand2_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index b4e11b32..75887ed3 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -259,5 +259,5 @@ class pnand3(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["nand3_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["nand3_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 8f7dcea4..87196342 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -237,6 +237,6 @@ class pnor2(pgate.pgate): """Computes effective capacitance. Results in fF""" c_load = load c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff - transistion_prob = spice["nor2_transisition_prob"] - return transistion_prob*(c_load + c_para) + transition_prob = spice["nor2_transition_prob"] + return transition_prob*(c_load + c_para) diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index 015b434a..0e1cd88f 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -12,12 +12,17 @@ class single_level_column_mux(design.design): Creates a single columnmux cell. """ - def __init__(self, tx_size): - name="single_level_column_mux_{}".format(tx_size) + unique_id = 1 + + def __init__(self, tx_size, bitcell_bl="bl", bitcell_br="br"): + name="single_level_column_mux_{}_no{}".format(tx_size,single_level_column_mux.unique_id) + single_level_column_mux.unique_id += 1 design.design.__init__(self, name) debug.info(2, "create single column mux cell: {0}".format(name)) self.tx_size = tx_size + self.bitcell_bl = bitcell_bl + self.bitcell_br = bitcell_br self.create_netlist() if not OPTS.netlist_only: @@ -59,8 +64,8 @@ class single_level_column_mux(design.design): def add_bitline_pins(self): """ Add the top and bottom pins to this cell """ - bl_pos = vector(self.bitcell.get_pin("bl").lx(), 0) - br_pos = vector(self.bitcell.get_pin("br").lx(), 0) + bl_pos = vector(self.bitcell.get_pin(self.bitcell_bl).lx(), 0) + br_pos = vector(self.bitcell.get_pin(self.bitcell_br).lx(), 0) # bl and br self.add_layout_pin(text="bl", diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index 03791089..1eaa6abb 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -34,7 +34,9 @@ class sram_1bank(sram_base): self.bank_inst=self.create_bank(0) - self.control_logic_inst = self.create_control_logic() + self.control_logic_inst = [None] * self.total_ports + for port in range(self.total_ports): + self.control_logic_inst[port] = self.create_control_logic(port) self.row_addr_dff_inst = self.create_row_addr_dff() @@ -59,11 +61,11 @@ class sram_1bank(sram_base): # up to the row address DFFs. control_pos = vector(-self.control_logic.width - 2*self.m2_pitch, self.bank.bank_center.y - self.control_logic.control_logic_center.y) - self.control_logic_inst.place(control_pos) + self.control_logic_inst[0].place(control_pos) # The row address bits are placed above the control logic aligned on the right. - row_addr_pos = vector(self.control_logic_inst.rx() - self.row_addr_dff.width, - self.control_logic_inst.uy()) + row_addr_pos = vector(self.control_logic_inst[0].rx() - self.row_addr_dff.width, + self.control_logic_inst[0].uy()) self.row_addr_dff_inst.place(row_addr_pos) # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk @@ -95,7 +97,7 @@ class sram_1bank(sram_base): """ # Connect the control pins as inputs for n in self.control_logic_inputs + ["clk"]: - self.copy_layout_pin(self.control_logic_inst, n) + self.copy_layout_pin(self.control_logic_inst[0], n) for i in range(self.word_size): dout_name = "dout0[{}]".format(i) @@ -134,7 +136,7 @@ class sram_1bank(sram_base): """ Route the clock network """ # This is the actual input to the SRAM - self.copy_layout_pin(self.control_logic_inst, "clk") + self.copy_layout_pin(self.control_logic_inst[0], "clk") # Connect all of these clock pins to the clock in the central bus # This is something like a "spine" clock distribution. The two spines @@ -158,7 +160,7 @@ class sram_1bank(sram_base): # This uses a metal2 track to the right of the control/row addr DFF # to route vertically. - control_clk_buf_pin = self.control_logic_inst.get_pin("clk_buf") + control_clk_buf_pin = self.control_logic_inst[0].get_pin("clk_buf") control_clk_buf_pos = control_clk_buf_pin.rc() row_addr_clk_pin = self.row_addr_dff_inst.get_pin("clk") row_addr_clk_pos = row_addr_clk_pin.rc() @@ -177,7 +179,7 @@ class sram_1bank(sram_base): top_instances = [self.bank_inst, self.row_addr_dff_inst, self.data_dff_inst, - self.control_logic_inst] + self.control_logic_inst[0]] if self.col_addr_dff: top_instances.append(self.col_addr_dff_inst) @@ -193,7 +195,7 @@ class sram_1bank(sram_base): top_instances = [self.bank_inst, self.row_addr_dff_inst, self.data_dff_inst, - self.control_logic_inst] + self.control_logic_inst[0]] if self.col_addr_dff: top_instances.append(self.col_addr_dff_inst) @@ -267,7 +269,7 @@ class sram_1bank(sram_base): def route_control_logic(self): """ Route the outputs from the control logic module """ for n in self.control_logic_outputs: - src_pin = self.control_logic_inst.get_pin(n) + src_pin = self.control_logic_inst[0].get_pin(n) dest_pin = self.bank_inst.get_pin(n) self.connect_rail_from_left_m2m3(src_pin, dest_pin) self.add_via_center(layers=("metal1","via1","metal2"), @@ -319,8 +321,10 @@ class sram_1bank(sram_base): route_map = list(zip(bank_names, dff_names)) dff_pins = {key: self.data_dff_inst.get_pin(key) for key in dff_names } - bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names } - self.create_horizontal_channel_route(route_map, dff_pins, bank_pins, offset) + bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names } + # Combine the dff and bank pins into a single dictionary of pin name to pin. + all_pins = {**dff_pins, **bank_pins} + self.create_horizontal_channel_route(route_map, all_pins, offset) @@ -332,7 +336,7 @@ class sram_1bank(sram_base): """ for n in self.control_logic_outputs: - pin = self.control_logic_inst.get_pin(n) + pin = self.control_logic_inst[0].get_pin(n) self.add_label(text=n, layer=pin.layer, offset=pin.center()) diff --git a/compiler/sram_base.py b/compiler/sram_base.py index ca3351b5..9a511bd4 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -28,6 +28,16 @@ class sram_base(design): def add_pins(self): """ Add pins for entire SRAM. """ + self.read_index = [] + port_number = 0 + for port in range(OPTS.num_rw_ports): + self.read_index.append("{}".format(port_number)) + port_number += 1 + for port in range(OPTS.num_w_ports): + port_number += 1 + for port in range(OPTS.num_r_ports): + self.read_index.append("{}".format(port_number)) + port_number += 1 for port in range(self.total_write): for bit in range(self.word_size): @@ -41,11 +51,15 @@ class sram_base(design): self.control_logic_inputs=self.control_logic.get_inputs() self.control_logic_outputs=self.control_logic.get_outputs() - self.add_pin_list(self.control_logic_inputs,"INPUT") + #self.add_pin_list(self.control_logic_inputs,"INPUT") + self.add_pin("csb","INPUT") + for port in range(self.total_write): + self.add_pin("web{}".format(port),"INPUT") + self.add_pin("clk","INPUT") for port in range(self.total_read): for bit in range(self.word_size): - self.add_pin("DOUT{0}[{1}]".format(port,bit),"OUTPUT") + self.add_pin("DOUT{0}[{1}]".format(self.read_index[port],bit),"OUTPUT") self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") @@ -213,10 +227,6 @@ class sram_base(design): c = reload(__import__(OPTS.control_logic)) self.mod_control_logic = getattr(c, OPTS.control_logic) - c = reload(__import__(OPTS.ms_flop)) - self.mod_ms_flop = getattr(c, OPTS.ms_flop) - self.ms_flop = self.mod_ms_flop() - from control_logic import control_logic # Create the control logic module @@ -234,7 +244,7 @@ class sram_base(design): else: self.col_addr_dff = None - self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size*self.total_ports) + self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size*self.total_write) self.add_mod(self.data_dff) # Create the bank module (up to four are instantiated) @@ -262,7 +272,7 @@ class sram_base(design): temp = [] for port in range(self.total_read): for bit in range(self.word_size): - temp.append("DOUT{0}[{1}]".format(port,bit)) + temp.append("DOUT{0}[{1}]".format(self.read_index[port],bit)) for port in range(self.total_write): for bit in range(self.word_size): temp.append("BANK_DIN{0}[{1}]".format(port,bit)) @@ -273,7 +283,7 @@ class sram_base(design): for port in range(self.total_ports): temp.append("bank_sel{0}[{1}]".format(port,bank_num)) for port in range(self.total_read): - temp.append("s_en{0}".format(port)) + temp.append("s_en{0}".format(self.read_index[port])) for port in range(self.total_write): temp.append("w_en{0}".format(port)) temp.extend(["clk_buf_bar","clk_buf" , "vdd", "gnd"]) @@ -321,10 +331,10 @@ class sram_base(design): # inputs, outputs/output/bar inputs = [] outputs = [] - for k in range(self.total_ports): + for port in range(self.total_ports): for i in range(self.row_addr_size): - inputs.append("ADDR{}[{}]".format(k,i+self.col_addr_size)) - outputs.append("A{}[{}]".format(k,i+self.col_addr_size)) + inputs.append("ADDR{}[{}]".format(port,i+self.col_addr_size)) + outputs.append("A{}[{}]".format(port,i+self.col_addr_size)) self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"]) return inst @@ -337,10 +347,10 @@ class sram_base(design): # inputs, outputs/output/bar inputs = [] outputs = [] - for k in range(self.total_ports): + for port in range(self.total_ports): for i in range(self.col_addr_size): - inputs.append("ADDR{}[{}]".format(k,i)) - outputs.append("A{}[{}]".format(k,i)) + inputs.append("ADDR{}[{}]".format(port,i)) + outputs.append("A{}[{}]".format(port,i)) self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"]) return inst @@ -353,20 +363,24 @@ class sram_base(design): # inputs, outputs/output/bar inputs = [] outputs = [] - for k in range(self.total_write): + for port in range(self.total_write): for i in range(self.word_size): - inputs.append("DIN{}[{}]".format(k,i)) - outputs.append("BANK_DIN{}[{}]".format(k,i)) + inputs.append("DIN{}[{}]".format(port,i)) + outputs.append("BANK_DIN{}[{}]".format(port,i)) self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"]) return inst - def create_control_logic(self): + def create_control_logic(self, port): """ Add and place control logic """ inst = self.add_inst(name="control", mod=self.control_logic) - self.connect_inst(self.control_logic_inputs + self.control_logic_outputs + ["vdd", "gnd"]) + self.connect_inst(["csb", "web{}".format(port), "clk", + "s_en{}".format(port), "w_en{}".format(port), "clk_buf_bar", "clk_buf", + "vdd", "gnd"]) + + #self.connect_inst(self.control_logic_inputs + self.control_logic_outputs + ["vdd", "gnd"]) return inst diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 8e44aa52..a68585bb 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -17,24 +17,25 @@ class precharge_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import precharge import tech - + debug.info(2, "Checking precharge for handmade bitcell") tx = precharge.precharge(name="precharge_driver", size=1) self.local_check(tx) - debug.info(2, "Checking precharge for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 2 - OPTS.num_r_ports = 2 - OPTS.num_w_ports = 2 - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="rwbl0", bitcell_br="rwbl_bar0") - self.local_check(tx) - - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="wbl0", bitcell_br="wbl_bar0") - self.local_check(tx) - - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="rbl0", bitcell_br="rbl_bar0") - self.local_check(tx) + if OPTS.multiport_check: + debug.info(2, "Checking precharge for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(tx) + + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 01dc4445..6437c58d 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -23,6 +23,21 @@ class single_level_column_mux_test(openram_test): debug.info(2, "Checking column mux") tx = single_level_column_mux.single_level_column_mux(tx_size=8) self.local_check(tx) + + if OPTS.multiport_check: + debug.info(2, "Checking column mux for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(tx) + + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index ea231292..77a1358e 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -27,6 +27,33 @@ class single_level_column_mux_test(openram_test): debug.info(1, "Testing sample for 8-way column_mux_array") a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4) self.local_check(a) + + if OPTS.multiport_check: + debug.info(2, "Checking column mux array for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + debug.info(1, "Testing sample for 2-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 4-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 49530410..1e82c69b 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -22,20 +22,21 @@ class precharge_test(openram_test): pc = precharge_array.precharge_array(columns=3) self.local_check(pc) - debug.info(2, "Checking precharge for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 2 - OPTS.num_r_ports = 2 - OPTS.num_w_ports = 2 - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="rwbl0", bitcell_br="rwbl_bar0") - self.local_check(pc) - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="wbl0", bitcell_br="wbl_bar0") - self.local_check(pc) - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="rbl0", bitcell_br="rbl_bar0") - self.local_check(pc) + if OPTS.multiport_check: + debug.info(2, "Checking precharge array for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(pc) + + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(pc) + + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(pc) globals.end_openram() diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index 3a19a2ec..f69a3c02 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,20 +20,19 @@ class wordline_driver_test(openram_test): import wordline_driver import tech - # check wordline driver array in single port debug.info(2, "Checking driver") tx = wordline_driver.wordline_driver(rows=8) self.local_check(tx) - # check wordline driver array in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Checking driver (multi-port case)") - tx = wordline_driver.wordline_driver(rows=8) - self.local_check(tx) + if OPTS.multiport_check: + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Checking driver (multi-port case)") + tx = wordline_driver.wordline_driver(rows=8) + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index f6f9e14f..d167a752 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -17,7 +17,6 @@ class sense_amp_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import sense_amp_array - # check sense amp array in single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) self.local_check(a) @@ -26,19 +25,19 @@ class sense_amp_test(openram_test): a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) self.local_check(a) - # check sense amp array in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") - a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) - self.local_check(a) + if OPTS.multiport_check: + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") + a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) + self.local_check(a) - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") - a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) - self.local_check(a) + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") + a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 67978f11..7ede24dd 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -17,7 +17,6 @@ class write_driver_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import write_driver_array - # check write driver array in single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") a = write_driver_array.write_driver_array(columns=8, word_size=8) self.local_check(a) @@ -26,19 +25,19 @@ class write_driver_test(openram_test): a = write_driver_array.write_driver_array(columns=16, word_size=8) self.local_check(a) - # check write driver array in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(columns=8, word_size=8) - self.local_check(a) + if OPTS.multiport_check: + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") + a = write_driver_array.write_driver_array(columns=8, word_size=8) + self.local_check(a) - debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(columns=16, word_size=8) - self.local_check(a) + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") + a = write_driver_array.write_driver_array(columns=16, word_size=8) + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/11_ms_flop_array_test.py b/compiler/tests/11_ms_flop_array_test.py deleted file mode 100755 index d6472a15..00000000 --- a/compiler/tests/11_ms_flop_array_test.py +++ /dev/null @@ -1,35 +0,0 @@ -#!/usr/bin/env python3 -""" -Run a regression test on a dff_array. -""" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -from globals import OPTS -import debug - -class dff_array_test(openram_test): - - def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ms_flop_array - - debug.info(2, "Testing ms_flop_array for columns=8, word_size=8") - a = ms_flop_array.ms_flop_array(columns=8, word_size=8) - self.local_check(a) - - debug.info(2, "Testing ms_flop_array for columns=16, word_size=8") - a = ms_flop_array.ms_flop_array(columns=16, word_size=8) - self.local_check(a) - - globals.end_openram() - -# instantiate a copdsay of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index f377a3db..5ff00f1b 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -33,6 +33,25 @@ class psingle_bank_test(openram_test): debug.info(1, "No column mux") a = bank(c, name="bank1_1rw_0w_0r_single") self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + debug.info(1, "Two way column mux") + a = bank(c, name="bank1_1rw_0w_0r_single") + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + debug.info(1, "Four way column mux") + a = bank(c, name="bank1_1rw_0w_0r_single") + self.local_check(a) + + c.num_words=128 + c.words_per_row=8 + debug.info(1, "Four way column mux") + a = bank(c, name="bank1_1rw_0w_0r_single") + self.local_check(a) + """ # multiport can't generate layout yet on the bank level OPTS.netlist_only = True @@ -120,7 +139,7 @@ class psingle_bank_test(openram_test): self.local_check(a) """ - globals.end_openram() + #globals.end_openram() # instantiate a copy of the class to actually run the test if __name__ == "__main__": diff --git a/compiler/tests/20_psram_1bank_test.py b/compiler/tests/20_psram_1bank_test.py new file mode 100755 index 00000000..a1ccd8e2 --- /dev/null +++ b/compiler/tests/20_psram_1bank_test.py @@ -0,0 +1,73 @@ +#!/usr/bin/env python3 +""" +Run a regression test on a 1 bank SRAM +""" + +import unittest +from testutils import header,openram_test +import sys,os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") +class sram_1bank_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + from sram import sram + from sram_config import sram_config + OPTS.bitcell = "pbitcell" + + # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent) + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + c = sram_config(word_size=4, + num_words=16, + num_banks=1) + c.words_per_row=1 + + debug.info(1, "Single bank, no column mux with control logic") + a = sram(c, "sram1") + self.local_check(a, final_verification=True) + + """ + OPTS.rw_ports = 1 + OPTS.w_ports = 1 + OPTS.r_ports = 1 + OPTS.netlist_only = True + + debug.info(1, "Single bank, no column mux with control logic") + a = sram(c, "sram1") + self.local_check(a, final_verification=True) + + c.num_words=32 + c.words_per_row=2 + debug.info(1, "Single bank two way column mux with control logic") + a = sram(c, "sram2") + self.local_check(a, final_verification=True) + + c.num_words=64 + c.words_per_row=4 + debug.info(1, "Single bank, four way column mux with control logic") + a = sram(c, "sram3") + self.local_check(a, final_verification=True) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + debug.info(1, "Single bank, eight way column mux with control logic") + a = sram(c, "sram4") + self.local_check(a, final_verification=True) + """ + #globals.end_openram() + +# instantiate a copy of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 93fc8413..da59c447 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -50,28 +50,29 @@ class timing_sram_test(openram_test): slews = [tech.spice["rise_time"]*2] data = d.analyze(probe_address, probe_data, slews, loads) + #Assumes single rw port (6t sram) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.5829000000000004], - 'delay_lh': [0.2255964], + golden_data = {'delay_hl0': [2.5829000000000004], + 'delay_lh0': [0.2255964], 'leakage_power': 0.0019498999999999996, 'min_period': 4.844, - 'read0_power': [0.055371399999999994], - 'read1_power': [0.0520225], - 'slew_hl': [0.0794261], - 'slew_lh': [0.0236264], - 'write0_power': [0.06545659999999999], - 'write1_power': [0.057846299999999996]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [4.0249], - 'delay_lh': [2.2611], - 'leakage_power': 0.0257389, + 'read0_power0': [0.055371399999999994], + 'read1_power0': [0.0520225], + 'slew_hl0': [0.0794261], + 'slew_lh0': [0.0236264], + 'write0_power0': [0.06545659999999999], + 'write1_power0': [0.057846299999999996]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'delay_hl0': [3.452], + 'delay_lh0': [1.3792000000000002], + 'leakage_power': 0.0257065, 'min_period': 4.688, - 'read0_power': [24.9279], - 'read1_power': [24.0219], - 'slew_hl': [0.8500753999999999], - 'slew_lh': [0.4122653], - 'write0_power': [28.197600000000005], - 'write1_power': [25.685]} + 'read0_power0': [15.0755], + 'read1_power0': [14.4526], + 'slew_hl0': [0.6137363], + 'slew_lh0': [0.3381045], + 'write0_power0': [16.9203], + 'write1_power0': [15.367]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index b123ed57..2969f95e 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -35,15 +35,15 @@ class timing_setup_test(openram_test): data = sh.analyze(slews,slews) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'setup_times_LH': [0.014648399999999999], - 'hold_times_LH': [0.0024414], - 'hold_times_HL': [-0.0036620999999999997], - 'setup_times_HL': [0.0085449]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'setup_times_LH': [0.08178709999999999], - 'hold_times_LH': [0.0024414], - 'hold_times_HL': [-0.0646973], - 'setup_times_HL': [0.0390625]} + golden_data = {'hold_times_HL': [-0.0097656], + 'hold_times_LH': [-0.0158691], + 'setup_times_HL': [0.026855499999999997], + 'setup_times_LH': [0.032959]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'hold_times_HL': [-0.0891113], + 'hold_times_LH': [-0.0769043], + 'setup_times_HL': [0.1184082], + 'setup_times_LH': [0.1733398]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index d54cdf54..cf7f096b 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -51,27 +51,27 @@ class timing_sram_test(openram_test): data = d.analyze(probe_address, probe_data, slews, loads) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.584251], - 'delay_lh': [0.22870469999999998], + golden_data = {'delay_hl0': [2.584251], + 'delay_lh0': [0.22870469999999998], 'leakage_power': 0.0009567935, 'min_period': 4.844, - 'read0_power': [0.0547588], - 'read1_power': [0.051159970000000006], - 'slew_hl': [0.08164099999999999], - 'slew_lh': [0.025474979999999998], - 'write0_power': [0.06513271999999999], - 'write1_power': [0.058057000000000004]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'delay_hl': [4.221382999999999], - 'delay_lh': [2.6459520000000003], - 'leakage_power': 0.0013865260000000001, + 'read0_power0': [0.0547588], + 'read1_power0': [0.051159970000000006], + 'slew_hl0': [0.08164099999999999], + 'slew_lh0': [0.025474979999999998], + 'write0_power0': [0.06513271999999999], + 'write1_power0': [0.058057000000000004]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'delay_hl0': [3.644147], + 'delay_lh0': [1.629815], + 'leakage_power': 0.0009299118999999999, 'min_period': 4.688, - 'read0_power': [26.699669999999998], - 'read1_power': [26.13123], - 'slew_hl': [0.9821776000000001], - 'slew_lh': [1.5791520000000001], - 'write0_power': [30.71939], - 'write1_power': [27.44753]} + 'read0_power0': [16.28732], + 'read1_power0': [15.75155], + 'slew_hl0': [0.6722473], + 'slew_lh0': [0.3386347], + 'write0_power0': [18.545450000000002], + 'write1_power0': [16.81084]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 849a23f0..d86fcb23 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -35,15 +35,15 @@ class timing_setup_test(openram_test): data = sh.analyze(slews,slews) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'setup_times_LH': [0.01464844], - 'hold_times_LH': [0.0024414059999999997], - 'hold_times_HL': [-0.003662109], - 'setup_times_HL': [0.008544922]} - elif OPTS.tech_name == "scn3me_subm": - golden_data = {'setup_times_LH': [0.07568359], - 'hold_times_LH': [0.008544922], - 'hold_times_HL': [-0.05859374999999999], - 'setup_times_HL': [0.03295898]} + golden_data = {'hold_times_HL': [-0.01586914], + 'hold_times_LH': [-0.01586914], + 'setup_times_HL': [0.02685547], + 'setup_times_LH': [0.03295898]} + elif OPTS.tech_name == "scn4m_subm": + golden_data = {'hold_times_HL': [-0.08911132999999999], + 'hold_times_LH': [-0.0769043], + 'setup_times_HL': [0.1184082], + 'setup_times_LH': [0.1672363]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/config_20_scn4m_subm.py b/compiler/tests/config_20_scn4m_subm.py new file mode 100644 index 00000000..5715d49f --- /dev/null +++ b/compiler/tests/config_20_scn4m_subm.py @@ -0,0 +1,13 @@ +word_size = 1 +num_words = 16 +num_banks = 1 + +tech_name = "scn4m_subm" +process_corners = ["TT"] +supply_voltages = [5.0] +temperatures = [25] + +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic" + diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cf9df15f..84f301f8 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index c14afc35..2fbbd8b8 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index 1cd10b44..a3ec121c 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib index f43c12c7..e6aa54f9 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + direction : input; + capacitance : 9.8242; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 78.5936; min_capacitance : 2.45605; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){ } } - pin(OEb){ - direction : input; - capacitance : 9.8242; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132"); - } - } - } - pin(WEb){ direction : input; capacitance : 9.8242; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib index 6e6c9501..8d774ce5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib @@ -87,20 +87,20 @@ cell (sram_2_16_1_scn3me_subm){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + direction : input; + capacitance : 9.8242; memory_write(){ - address : ADDR; + address : ADDR0; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 78.5936; min_capacitance : 2.45605; memory_read(){ - address : ADDR; + address : ADDR0; } pin(DOUT[1:0]){ timing(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){ } } - pin(OEb){ - direction : input; - capacitance : 9.8242; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - pin(WEb){ direction : input; capacitance : 9.8242; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib index 39924746..b514a858 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + direction : input; + capacitance : 9.8242; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 78.5936; min_capacitance : 2.45605; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){ } } - pin(OEb){ - direction : input; - capacitance : 9.8242; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132"); - } - } - } - pin(WEb){ direction : input; capacitance : 9.8242; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.lef b/compiler/tests/golden/sram_2_16_1_scn4m_subm.lef new file mode 100644 index 00000000..9d784677 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.lef @@ -0,0 +1,5533 @@ +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS +SITE MacroSite + CLASS Core ; + SIZE 148050.0 by 461850.0 ; +END MacroSite +MACRO sram_2_16_1_scn3me_subm + CLASS BLOCK ; + SIZE 148050.0 BY 461850.0 ; + SYMMETRY X Y R90 ; + SITE MacroSite ; + PIN DATA[0] + DIRECTION INOUT ; + PORT + LAYER metal2 ; + RECT 120900.0 0.0 121800.0 1800.0 ; + END + END DATA[0] + PIN DATA[1] + DIRECTION INOUT ; + PORT + LAYER metal2 ; + RECT 131100.0 0.0 132000.0 1800.0 ; + END + END DATA[1] + PIN ADDR[0] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 87600.0 10800.0 89100.0 ; + END + END ADDR[0] + PIN ADDR[1] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 77400.0 10800.0 78900.0 ; + END + END ADDR[1] + PIN ADDR[2] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 67200.0 10800.0 68700.0 ; + END + END ADDR[2] + PIN ADDR[3] + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT 0.0 57000.0 10800.0 58500.0 ; + END + END ADDR[3] + PIN CSb + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT -38400.0 182700.0 -36600.0 184500.0 ; + END + END CSb + PIN WEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT -28200.0 182700.0 -26400.0 184500.0 ; + END + END WEb + PIN OEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; + RECT -48600.0 182700.0 -46800.0 184500.0 ; + END + END OEb + PIN clk + DIRECTION INPUT ; + PORT + LAYER metal1 ; + RECT -10200.0 181800.0 -9000.0 185400.0 ; + END + END clk + PIN vdd + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal2 ; + RECT 4950.0 0.0 8550.0 461850.0 ; + LAYER metal2 ; + RECT 144450.0 0.0 148050.0 461850.0 ; + LAYER metal1 ; + RECT 0.0 4950.0 148050.0 8550.0 ; + LAYER metal1 ; + RECT 0.0 458250.0 148050.0 461850.0 ; + END + END vdd + PIN gnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal2 ; + RECT 0.0 0.0 3600.0 461850.0 ; + LAYER metal2 ; + RECT 139500.0 0.0 143100.0 461850.0 ; + LAYER metal1 ; + RECT 0.0 0.0 148050.0 3600.0 ; + LAYER metal1 ; + RECT 0.0 453300.0 148050.0 456900.0 ; + END + END gnd + OBS + LAYER metal1 ; + RECT 48300.0 215550.0 49200.0 216450.0 ; + RECT 48300.0 213150.0 49200.0 214050.0 ; + RECT 46950.0 215550.0 48750.0 216450.0 ; + RECT 48300.0 213600.0 49200.0 216000.0 ; + RECT 48750.0 213150.0 50700.0 214050.0 ; + RECT 100800.0 215550.0 101700.0 216450.0 ; + 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126150.0 81300.0 127050.0 ; + RECT 1800.0 153750.0 81300.0 154650.0 ; + RECT 1800.0 181350.0 81300.0 182250.0 ; + RECT 6750.0 112350.0 81300.0 113250.0 ; + RECT 6750.0 139950.0 81300.0 140850.0 ; + RECT 6750.0 167550.0 81300.0 168450.0 ; + RECT 6750.0 195150.0 81300.0 196050.0 ; + RECT 68700.0 87300.0 85800.0 88200.0 ; + RECT 68700.0 78600.0 88500.0 79500.0 ; + RECT 68700.0 66900.0 91200.0 67800.0 ; + RECT 68700.0 58200.0 93900.0 59100.0 ; + RECT 1800.0 82950.0 9900.0 83850.0 ; + RECT 1800.0 62550.0 9900.0 63450.0 ; + RECT 66300.0 50250.0 67200.0 51150.0 ; + RECT 66300.0 50700.0 67200.0 52800.0 ; + RECT 6750.0 50250.0 66750.0 51150.0 ; + RECT 104700.0 42300.0 116400.0 43200.0 ; + RECT 99300.0 37800.0 116400.0 38700.0 ; + RECT 102000.0 35400.0 116400.0 36300.0 ; + RECT 104700.0 438600.0 116400.0 439500.0 ; + RECT 107400.0 107100.0 116400.0 108000.0 ; + RECT 110100.0 205200.0 116400.0 206100.0 ; + RECT 12300.0 95250.0 13200.0 96150.0 ; + RECT 12300.0 93600.0 13200.0 95700.0 ; + RECT 12750.0 95250.0 96600.0 96150.0 ; + RECT 53850.0 431850.0 97500.0 432750.0 ; + RECT 116400.0 449700.0 146250.0 450600.0 ; + RECT 116400.0 177900.0 146250.0 178800.0 ; + RECT 116400.0 109200.0 146250.0 110100.0 ; + RECT 116400.0 96300.0 146250.0 97200.0 ; + RECT 116400.0 19500.0 146250.0 20400.0 ; + RECT 6750.0 222750.0 146250.0 223650.0 ; + RECT 6750.0 250350.0 146250.0 251250.0 ; + RECT 6750.0 277950.0 146250.0 278850.0 ; + RECT 6750.0 305550.0 146250.0 306450.0 ; + RECT 6750.0 333150.0 146250.0 334050.0 ; + RECT 6750.0 360750.0 146250.0 361650.0 ; + RECT 6750.0 388350.0 146250.0 389250.0 ; + RECT 6750.0 415950.0 146250.0 416850.0 ; + RECT 116400.0 33300.0 143100.0 34200.0 ; + RECT 116400.0 203100.0 143100.0 204000.0 ; + RECT 116400.0 105000.0 143100.0 105900.0 ; + RECT 1800.0 208950.0 57000.0 209850.0 ; + RECT 1800.0 236550.0 57000.0 237450.0 ; + RECT 1800.0 264150.0 57000.0 265050.0 ; + RECT 1800.0 291750.0 57000.0 292650.0 ; + RECT 1800.0 319350.0 57000.0 320250.0 ; + RECT 1800.0 346950.0 57000.0 347850.0 ; + RECT 1800.0 374550.0 57000.0 375450.0 ; + RECT 1800.0 402150.0 57000.0 403050.0 ; + RECT 1800.0 429750.0 57000.0 430650.0 ; + RECT 116400.0 209400.0 126600.0 223200.0 ; + RECT 116400.0 237000.0 126600.0 223200.0 ; + RECT 116400.0 237000.0 126600.0 250800.0 ; + RECT 116400.0 264600.0 126600.0 250800.0 ; + RECT 116400.0 264600.0 126600.0 278400.0 ; + RECT 116400.0 292200.0 126600.0 278400.0 ; + RECT 116400.0 292200.0 126600.0 306000.0 ; + RECT 116400.0 319800.0 126600.0 306000.0 ; + RECT 116400.0 319800.0 126600.0 333600.0 ; + RECT 116400.0 347400.0 126600.0 333600.0 ; + RECT 116400.0 347400.0 126600.0 361200.0 ; + RECT 116400.0 375000.0 126600.0 361200.0 ; + RECT 116400.0 375000.0 126600.0 388800.0 ; + RECT 116400.0 402600.0 126600.0 388800.0 ; + RECT 116400.0 402600.0 126600.0 416400.0 ; + RECT 116400.0 430200.0 126600.0 416400.0 ; + RECT 126600.0 209400.0 136800.0 223200.0 ; + RECT 126600.0 237000.0 136800.0 223200.0 ; + RECT 126600.0 237000.0 136800.0 250800.0 ; + RECT 126600.0 264600.0 136800.0 250800.0 ; + RECT 126600.0 264600.0 136800.0 278400.0 ; + RECT 126600.0 292200.0 136800.0 278400.0 ; + RECT 126600.0 292200.0 136800.0 306000.0 ; + RECT 126600.0 319800.0 136800.0 306000.0 ; + RECT 126600.0 319800.0 136800.0 333600.0 ; + RECT 126600.0 347400.0 136800.0 333600.0 ; + RECT 126600.0 347400.0 136800.0 361200.0 ; + RECT 126600.0 375000.0 136800.0 361200.0 ; + RECT 126600.0 375000.0 136800.0 388800.0 ; + RECT 126600.0 402600.0 136800.0 388800.0 ; + RECT 126600.0 402600.0 136800.0 416400.0 ; + RECT 126600.0 430200.0 136800.0 416400.0 ; + RECT 115800.0 210900.0 137400.0 212100.0 ; + RECT 115800.0 234300.0 137400.0 235500.0 ; + RECT 115800.0 238500.0 137400.0 239700.0 ; + RECT 115800.0 261900.0 137400.0 263100.0 ; + RECT 115800.0 266100.0 137400.0 267300.0 ; + RECT 115800.0 289500.0 137400.0 290700.0 ; + RECT 115800.0 293700.0 137400.0 294900.0 ; + RECT 115800.0 317100.0 137400.0 318300.0 ; + RECT 115800.0 321300.0 137400.0 322500.0 ; + RECT 115800.0 344700.0 137400.0 345900.0 ; + RECT 115800.0 348900.0 137400.0 350100.0 ; + RECT 115800.0 372300.0 137400.0 373500.0 ; + RECT 115800.0 376500.0 137400.0 377700.0 ; + RECT 115800.0 399900.0 137400.0 401100.0 ; + RECT 115800.0 404100.0 137400.0 405300.0 ; + RECT 115800.0 427500.0 137400.0 428700.0 ; + RECT 115800.0 222600.0 137400.0 223500.0 ; + RECT 115800.0 250200.0 137400.0 251100.0 ; + RECT 115800.0 277800.0 137400.0 278700.0 ; + RECT 115800.0 305400.0 137400.0 306300.0 ; + RECT 115800.0 333000.0 137400.0 333900.0 ; + RECT 115800.0 360600.0 137400.0 361500.0 ; + RECT 115800.0 388200.0 137400.0 389100.0 ; + RECT 115800.0 415800.0 137400.0 416700.0 ; + RECT 121800.0 443400.0 123000.0 450600.0 ; + RECT 119400.0 436200.0 120600.0 437400.0 ; + RECT 121800.0 436200.0 123000.0 437400.0 ; + RECT 121800.0 436200.0 123000.0 437400.0 ; + RECT 119400.0 436200.0 120600.0 437400.0 ; + RECT 119400.0 443400.0 120600.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 119400.0 443400.0 120600.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 124200.0 443400.0 125400.0 444600.0 ; + RECT 124200.0 443400.0 125400.0 444600.0 ; + RECT 121800.0 443400.0 123000.0 444600.0 ; + RECT 121500.0 438450.0 120300.0 439650.0 ; + RECT 121800.0 448800.0 123000.0 450000.0 ; + RECT 119400.0 436200.0 120600.0 437400.0 ; + RECT 121800.0 436200.0 123000.0 437400.0 ; + RECT 119400.0 443400.0 120600.0 444600.0 ; + RECT 124200.0 443400.0 125400.0 444600.0 ; + RECT 116400.0 438600.0 126600.0 439500.0 ; + RECT 116400.0 449700.0 126600.0 450600.0 ; + RECT 132000.0 443400.0 133200.0 450600.0 ; + RECT 129600.0 436200.0 130800.0 437400.0 ; + RECT 132000.0 436200.0 133200.0 437400.0 ; + RECT 132000.0 436200.0 133200.0 437400.0 ; + RECT 129600.0 436200.0 130800.0 437400.0 ; + RECT 129600.0 443400.0 130800.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 129600.0 443400.0 130800.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 134400.0 443400.0 135600.0 444600.0 ; + RECT 134400.0 443400.0 135600.0 444600.0 ; + RECT 132000.0 443400.0 133200.0 444600.0 ; + RECT 131700.0 438450.0 130500.0 439650.0 ; + RECT 132000.0 448800.0 133200.0 450000.0 ; + RECT 129600.0 436200.0 130800.0 437400.0 ; + RECT 132000.0 436200.0 133200.0 437400.0 ; + RECT 129600.0 443400.0 130800.0 444600.0 ; + RECT 134400.0 443400.0 135600.0 444600.0 ; + RECT 126600.0 438600.0 136800.0 439500.0 ; + RECT 126600.0 449700.0 136800.0 450600.0 ; + RECT 116400.0 438600.0 136800.0 439500.0 ; + RECT 116400.0 449700.0 136800.0 450600.0 ; + RECT 116400.0 160500.0 126600.0 209400.0 ; + RECT 126600.0 160500.0 136800.0 209400.0 ; + RECT 116400.0 205200.0 136800.0 206100.0 ; + RECT 116400.0 177900.0 136800.0 178800.0 ; + RECT 116400.0 203100.0 136800.0 204000.0 ; + RECT 116400.0 99900.0 126600.0 160500.0 ; + RECT 126600.0 99900.0 136800.0 160500.0 ; + RECT 116400.0 107100.0 136800.0 108000.0 ; + RECT 116400.0 109200.0 136800.0 110100.0 ; + RECT 116400.0 105000.0 136800.0 105900.0 ; + RECT 116400.0 39900.0 126600.0 99900.0 ; + RECT 136800.0 39900.0 126600.0 99900.0 ; + RECT 116400.0 42300.0 136800.0 43200.0 ; + RECT 116400.0 96300.0 136800.0 97200.0 ; + RECT 116400.0 39900.0 126600.0 18000.0 ; + RECT 126600.0 39900.0 136800.0 18000.0 ; + RECT 116400.0 36300.0 136800.0 35400.0 ; + RECT 116400.0 38700.0 136800.0 37800.0 ; + RECT 116400.0 20400.0 136800.0 19500.0 ; + RECT 116400.0 34200.0 136800.0 33300.0 ; + RECT 38550.0 216750.0 39450.0 217650.0 ; + RECT 38550.0 215550.0 39450.0 216450.0 ; + RECT 34500.0 216750.0 39000.0 217650.0 ; + RECT 38550.0 216000.0 39450.0 217200.0 ; + RECT 39000.0 215550.0 43500.0 216450.0 ; + RECT 38550.0 228750.0 39450.0 229650.0 ; + RECT 38550.0 229950.0 39450.0 230850.0 ; + RECT 34500.0 228750.0 39000.0 229650.0 ; + RECT 38550.0 229200.0 39450.0 230400.0 ; + RECT 39000.0 229950.0 43500.0 230850.0 ; + RECT 38550.0 244350.0 39450.0 245250.0 ; + RECT 38550.0 243150.0 39450.0 244050.0 ; + RECT 34500.0 244350.0 39000.0 245250.0 ; + RECT 38550.0 243600.0 39450.0 244800.0 ; + RECT 39000.0 243150.0 43500.0 244050.0 ; + RECT 38550.0 256350.0 39450.0 257250.0 ; + RECT 38550.0 257550.0 39450.0 258450.0 ; + RECT 34500.0 256350.0 39000.0 257250.0 ; + RECT 38550.0 256800.0 39450.0 258000.0 ; + RECT 39000.0 257550.0 43500.0 258450.0 ; + RECT 38550.0 271950.0 39450.0 272850.0 ; + RECT 38550.0 270750.0 39450.0 271650.0 ; + RECT 34500.0 271950.0 39000.0 272850.0 ; + RECT 38550.0 271200.0 39450.0 272400.0 ; + RECT 39000.0 270750.0 43500.0 271650.0 ; + RECT 38550.0 283950.0 39450.0 284850.0 ; + RECT 38550.0 285150.0 39450.0 286050.0 ; + RECT 34500.0 283950.0 39000.0 284850.0 ; + RECT 38550.0 284400.0 39450.0 285600.0 ; + RECT 39000.0 285150.0 43500.0 286050.0 ; + RECT 38550.0 299550.0 39450.0 300450.0 ; + RECT 38550.0 298350.0 39450.0 299250.0 ; + RECT 34500.0 299550.0 39000.0 300450.0 ; + RECT 38550.0 298800.0 39450.0 300000.0 ; + RECT 39000.0 298350.0 43500.0 299250.0 ; + RECT 38550.0 311550.0 39450.0 312450.0 ; + RECT 38550.0 312750.0 39450.0 313650.0 ; + RECT 34500.0 311550.0 39000.0 312450.0 ; + RECT 38550.0 312000.0 39450.0 313200.0 ; + RECT 39000.0 312750.0 43500.0 313650.0 ; + RECT 38550.0 327150.0 39450.0 328050.0 ; + RECT 38550.0 325950.0 39450.0 326850.0 ; + RECT 34500.0 327150.0 39000.0 328050.0 ; + RECT 38550.0 326400.0 39450.0 327600.0 ; + RECT 39000.0 325950.0 43500.0 326850.0 ; + RECT 38550.0 339150.0 39450.0 340050.0 ; + RECT 38550.0 340350.0 39450.0 341250.0 ; + RECT 34500.0 339150.0 39000.0 340050.0 ; + RECT 38550.0 339600.0 39450.0 340800.0 ; + RECT 39000.0 340350.0 43500.0 341250.0 ; + RECT 38550.0 354750.0 39450.0 355650.0 ; + RECT 38550.0 353550.0 39450.0 354450.0 ; + RECT 34500.0 354750.0 39000.0 355650.0 ; + RECT 38550.0 354000.0 39450.0 355200.0 ; + RECT 39000.0 353550.0 43500.0 354450.0 ; + RECT 38550.0 366750.0 39450.0 367650.0 ; + RECT 38550.0 367950.0 39450.0 368850.0 ; + RECT 34500.0 366750.0 39000.0 367650.0 ; + RECT 38550.0 367200.0 39450.0 368400.0 ; + RECT 39000.0 367950.0 43500.0 368850.0 ; + RECT 38550.0 382350.0 39450.0 383250.0 ; + RECT 38550.0 381150.0 39450.0 382050.0 ; + RECT 34500.0 382350.0 39000.0 383250.0 ; + RECT 38550.0 381600.0 39450.0 382800.0 ; + RECT 39000.0 381150.0 43500.0 382050.0 ; + RECT 38550.0 394350.0 39450.0 395250.0 ; + RECT 38550.0 395550.0 39450.0 396450.0 ; + RECT 34500.0 394350.0 39000.0 395250.0 ; + RECT 38550.0 394800.0 39450.0 396000.0 ; + RECT 39000.0 395550.0 43500.0 396450.0 ; + RECT 38550.0 409950.0 39450.0 410850.0 ; + RECT 38550.0 408750.0 39450.0 409650.0 ; + RECT 34500.0 409950.0 39000.0 410850.0 ; + RECT 38550.0 409200.0 39450.0 410400.0 ; + RECT 39000.0 408750.0 43500.0 409650.0 ; + RECT 38550.0 421950.0 39450.0 422850.0 ; + RECT 38550.0 423150.0 39450.0 424050.0 ; + RECT 34500.0 421950.0 39000.0 422850.0 ; + RECT 38550.0 422400.0 39450.0 423600.0 ; + RECT 39000.0 423150.0 43500.0 424050.0 ; + RECT 10350.0 105150.0 26700.0 106050.0 ; + RECT 12450.0 119550.0 26700.0 120450.0 ; + RECT 14550.0 132750.0 26700.0 133650.0 ; + RECT 16650.0 147150.0 26700.0 148050.0 ; + RECT 18750.0 160350.0 26700.0 161250.0 ; + RECT 20850.0 174750.0 26700.0 175650.0 ; + RECT 22950.0 187950.0 26700.0 188850.0 ; + RECT 25050.0 202350.0 26700.0 203250.0 ; + RECT 10350.0 216750.0 29100.0 217650.0 ; + RECT 18750.0 214050.0 32100.0 214950.0 ; + RECT 10350.0 228750.0 29100.0 229650.0 ; + RECT 20850.0 231450.0 32100.0 232350.0 ; + RECT 10350.0 244350.0 29100.0 245250.0 ; + RECT 22950.0 241650.0 32100.0 242550.0 ; + RECT 10350.0 256350.0 29100.0 257250.0 ; + RECT 25050.0 259050.0 32100.0 259950.0 ; + RECT 12450.0 271950.0 29100.0 272850.0 ; + RECT 18750.0 269250.0 32100.0 270150.0 ; + RECT 12450.0 283950.0 29100.0 284850.0 ; + RECT 20850.0 286650.0 32100.0 287550.0 ; + RECT 12450.0 299550.0 29100.0 300450.0 ; + RECT 22950.0 296850.0 32100.0 297750.0 ; + RECT 12450.0 311550.0 29100.0 312450.0 ; + RECT 25050.0 314250.0 32100.0 315150.0 ; + RECT 14550.0 327150.0 29100.0 328050.0 ; + RECT 18750.0 324450.0 32100.0 325350.0 ; + RECT 14550.0 339150.0 29100.0 340050.0 ; + RECT 20850.0 341850.0 32100.0 342750.0 ; + RECT 14550.0 354750.0 29100.0 355650.0 ; + RECT 22950.0 352050.0 32100.0 352950.0 ; + RECT 14550.0 366750.0 29100.0 367650.0 ; + RECT 25050.0 369450.0 32100.0 370350.0 ; + RECT 16650.0 382350.0 29100.0 383250.0 ; + RECT 18750.0 379650.0 32100.0 380550.0 ; + RECT 16650.0 394350.0 29100.0 395250.0 ; + RECT 20850.0 397050.0 32100.0 397950.0 ; + RECT 16650.0 409950.0 29100.0 410850.0 ; + RECT 22950.0 407250.0 32100.0 408150.0 ; + RECT 16650.0 421950.0 29100.0 422850.0 ; + RECT 25050.0 424650.0 32100.0 425550.0 ; + RECT 65250.0 105150.0 64350.0 106050.0 ; + RECT 65250.0 109650.0 64350.0 110550.0 ; + RECT 69450.0 105150.0 64800.0 106050.0 ; + RECT 65250.0 105600.0 64350.0 110100.0 ; + RECT 64800.0 109650.0 62250.0 110550.0 ; + RECT 80850.0 105150.0 72900.0 106050.0 ; + RECT 65250.0 119550.0 64350.0 120450.0 ; + RECT 65250.0 123450.0 64350.0 124350.0 ; + RECT 69450.0 119550.0 64800.0 120450.0 ; + RECT 65250.0 120000.0 64350.0 123900.0 ; + RECT 64800.0 123450.0 59250.0 124350.0 ; + RECT 77850.0 119550.0 72900.0 120450.0 ; + RECT 80850.0 128250.0 56250.0 129150.0 ; + RECT 77850.0 142050.0 53250.0 142950.0 ; + RECT 62250.0 106350.0 48300.0 107250.0 ; + RECT 59250.0 103650.0 45300.0 104550.0 ; + RECT 56250.0 118350.0 48300.0 119250.0 ; + RECT 59250.0 121050.0 45300.0 121950.0 ; + RECT 62250.0 133950.0 48300.0 134850.0 ; + RECT 53250.0 131250.0 45300.0 132150.0 ; + RECT 56250.0 145950.0 48300.0 146850.0 ; + RECT 53250.0 148650.0 45300.0 149550.0 ; + RECT 38850.0 106350.0 37950.0 107250.0 ; + RECT 38850.0 105150.0 37950.0 106050.0 ; + RECT 42900.0 106350.0 38400.0 107250.0 ; + RECT 38850.0 105600.0 37950.0 106800.0 ; + RECT 38400.0 105150.0 33900.0 106050.0 ; + RECT 38850.0 118350.0 37950.0 119250.0 ; + RECT 38850.0 119550.0 37950.0 120450.0 ; + RECT 42900.0 118350.0 38400.0 119250.0 ; + RECT 38850.0 118800.0 37950.0 120000.0 ; + RECT 38400.0 119550.0 33900.0 120450.0 ; + RECT 38850.0 133950.0 37950.0 134850.0 ; + RECT 38850.0 132750.0 37950.0 133650.0 ; + RECT 42900.0 133950.0 38400.0 134850.0 ; + RECT 38850.0 133200.0 37950.0 134400.0 ; + RECT 38400.0 132750.0 33900.0 133650.0 ; + RECT 38850.0 145950.0 37950.0 146850.0 ; + RECT 38850.0 147150.0 37950.0 148050.0 ; + RECT 42900.0 145950.0 38400.0 146850.0 ; + RECT 38850.0 146400.0 37950.0 147600.0 ; + RECT 38400.0 147150.0 33900.0 148050.0 ; + RECT 68700.0 110850.0 67500.0 112800.0 ; + RECT 68700.0 99000.0 67500.0 100950.0 ; + RECT 73500.0 100350.0 72300.0 98550.0 ; + RECT 73500.0 109650.0 72300.0 113250.0 ; + RECT 70800.0 100350.0 69900.0 109650.0 ; + RECT 73500.0 109650.0 72300.0 110850.0 ; + RECT 71100.0 109650.0 69900.0 110850.0 ; + RECT 71100.0 109650.0 69900.0 110850.0 ; + RECT 73500.0 109650.0 72300.0 110850.0 ; + RECT 73500.0 100350.0 72300.0 101550.0 ; + RECT 71100.0 100350.0 69900.0 101550.0 ; + RECT 71100.0 100350.0 69900.0 101550.0 ; + RECT 73500.0 100350.0 72300.0 101550.0 ; + RECT 68700.0 110250.0 67500.0 111450.0 ; + RECT 68700.0 100350.0 67500.0 101550.0 ; + RECT 72900.0 105000.0 71700.0 106200.0 ; + RECT 72900.0 105000.0 71700.0 106200.0 ; + RECT 70350.0 105150.0 69450.0 106050.0 ; + RECT 75300.0 112350.0 65700.0 113250.0 ; + RECT 75300.0 98550.0 65700.0 99450.0 ; + RECT 68700.0 114750.0 67500.0 112800.0 ; + RECT 68700.0 126600.0 67500.0 124650.0 ; + RECT 73500.0 125250.0 72300.0 127050.0 ; + RECT 73500.0 115950.0 72300.0 112350.0 ; + RECT 70800.0 125250.0 69900.0 115950.0 ; + RECT 73500.0 115950.0 72300.0 114750.0 ; + RECT 71100.0 115950.0 69900.0 114750.0 ; + RECT 71100.0 115950.0 69900.0 114750.0 ; + RECT 73500.0 115950.0 72300.0 114750.0 ; + RECT 73500.0 125250.0 72300.0 124050.0 ; + RECT 71100.0 125250.0 69900.0 124050.0 ; + RECT 71100.0 125250.0 69900.0 124050.0 ; + RECT 73500.0 125250.0 72300.0 124050.0 ; + RECT 68700.0 115350.0 67500.0 114150.0 ; + RECT 68700.0 125250.0 67500.0 124050.0 ; + RECT 72900.0 120600.0 71700.0 119400.0 ; + RECT 72900.0 120600.0 71700.0 119400.0 ; + RECT 70350.0 120450.0 69450.0 119550.0 ; + RECT 75300.0 113250.0 65700.0 112350.0 ; + RECT 75300.0 127050.0 65700.0 126150.0 ; + RECT 29700.0 110850.0 28500.0 112800.0 ; + RECT 29700.0 99000.0 28500.0 100950.0 ; + RECT 34500.0 100350.0 33300.0 98550.0 ; + RECT 34500.0 109650.0 33300.0 113250.0 ; + RECT 31800.0 100350.0 30900.0 109650.0 ; + RECT 34500.0 109650.0 33300.0 110850.0 ; + RECT 32100.0 109650.0 30900.0 110850.0 ; + RECT 32100.0 109650.0 30900.0 110850.0 ; + RECT 34500.0 109650.0 33300.0 110850.0 ; + RECT 34500.0 100350.0 33300.0 101550.0 ; + RECT 32100.0 100350.0 30900.0 101550.0 ; + RECT 32100.0 100350.0 30900.0 101550.0 ; + RECT 34500.0 100350.0 33300.0 101550.0 ; + RECT 29700.0 110250.0 28500.0 111450.0 ; + RECT 29700.0 100350.0 28500.0 101550.0 ; + RECT 33900.0 105000.0 32700.0 106200.0 ; + RECT 33900.0 105000.0 32700.0 106200.0 ; + RECT 31350.0 105150.0 30450.0 106050.0 ; + RECT 36300.0 112350.0 26700.0 113250.0 ; + RECT 36300.0 98550.0 26700.0 99450.0 ; + RECT 29700.0 114750.0 28500.0 112800.0 ; + RECT 29700.0 126600.0 28500.0 124650.0 ; + RECT 34500.0 125250.0 33300.0 127050.0 ; + RECT 34500.0 115950.0 33300.0 112350.0 ; + RECT 31800.0 125250.0 30900.0 115950.0 ; + RECT 34500.0 115950.0 33300.0 114750.0 ; + RECT 32100.0 115950.0 30900.0 114750.0 ; + RECT 32100.0 115950.0 30900.0 114750.0 ; + RECT 34500.0 115950.0 33300.0 114750.0 ; + RECT 34500.0 125250.0 33300.0 124050.0 ; + RECT 32100.0 125250.0 30900.0 124050.0 ; + RECT 32100.0 125250.0 30900.0 124050.0 ; + RECT 34500.0 125250.0 33300.0 124050.0 ; + RECT 29700.0 115350.0 28500.0 114150.0 ; + RECT 29700.0 125250.0 28500.0 124050.0 ; + RECT 33900.0 120600.0 32700.0 119400.0 ; + RECT 33900.0 120600.0 32700.0 119400.0 ; + RECT 31350.0 120450.0 30450.0 119550.0 ; + RECT 36300.0 113250.0 26700.0 112350.0 ; + RECT 36300.0 127050.0 26700.0 126150.0 ; + RECT 29700.0 138450.0 28500.0 140400.0 ; + RECT 29700.0 126600.0 28500.0 128550.0 ; + RECT 34500.0 127950.0 33300.0 126150.0 ; + RECT 34500.0 137250.0 33300.0 140850.0 ; + RECT 31800.0 127950.0 30900.0 137250.0 ; + RECT 34500.0 137250.0 33300.0 138450.0 ; + RECT 32100.0 137250.0 30900.0 138450.0 ; + RECT 32100.0 137250.0 30900.0 138450.0 ; + RECT 34500.0 137250.0 33300.0 138450.0 ; + RECT 34500.0 127950.0 33300.0 129150.0 ; + RECT 32100.0 127950.0 30900.0 129150.0 ; + RECT 32100.0 127950.0 30900.0 129150.0 ; + RECT 34500.0 127950.0 33300.0 129150.0 ; + RECT 29700.0 137850.0 28500.0 139050.0 ; + RECT 29700.0 127950.0 28500.0 129150.0 ; + RECT 33900.0 132600.0 32700.0 133800.0 ; + RECT 33900.0 132600.0 32700.0 133800.0 ; + RECT 31350.0 132750.0 30450.0 133650.0 ; + RECT 36300.0 139950.0 26700.0 140850.0 ; + RECT 36300.0 126150.0 26700.0 127050.0 ; + RECT 29700.0 142350.0 28500.0 140400.0 ; + RECT 29700.0 154200.0 28500.0 152250.0 ; + RECT 34500.0 152850.0 33300.0 154650.0 ; + RECT 34500.0 143550.0 33300.0 139950.0 ; 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46500.0 109650.0 45300.0 110850.0 ; + RECT 48900.0 109650.0 47700.0 110850.0 ; + RECT 46500.0 109650.0 45300.0 110850.0 ; + RECT 44100.0 109650.0 42900.0 110850.0 ; + RECT 44100.0 109650.0 42900.0 110850.0 ; + RECT 46500.0 109650.0 45300.0 110850.0 ; + RECT 48900.0 100950.0 47700.0 102150.0 ; + RECT 46500.0 100950.0 45300.0 102150.0 ; + RECT 46500.0 100950.0 45300.0 102150.0 ; + RECT 48900.0 100950.0 47700.0 102150.0 ; + RECT 46500.0 100950.0 45300.0 102150.0 ; + RECT 44100.0 100950.0 42900.0 102150.0 ; + RECT 44100.0 100950.0 42900.0 102150.0 ; + RECT 46500.0 100950.0 45300.0 102150.0 ; + RECT 41700.0 110250.0 40500.0 111450.0 ; + RECT 41700.0 100350.0 40500.0 101550.0 ; + RECT 44100.0 103500.0 45300.0 104700.0 ; + RECT 47100.0 106200.0 48300.0 107400.0 ; + RECT 46500.0 109650.0 45300.0 110850.0 ; + RECT 44100.0 100950.0 42900.0 102150.0 ; + RECT 42900.0 106200.0 44100.0 107400.0 ; + RECT 48300.0 106200.0 47100.0 107400.0 ; + RECT 45300.0 103500.0 44100.0 104700.0 ; + RECT 44100.0 106200.0 42900.0 107400.0 ; + RECT 50700.0 112350.0 36300.0 113250.0 ; + RECT 50700.0 98550.0 36300.0 99450.0 ; + RECT 48900.0 124650.0 47700.0 127050.0 ; + RECT 48900.0 115950.0 47700.0 112350.0 ; + RECT 44100.0 115950.0 42900.0 112350.0 ; + RECT 41700.0 114750.0 40500.0 112800.0 ; + RECT 41700.0 126600.0 40500.0 124650.0 ; + RECT 48900.0 115950.0 47700.0 114750.0 ; + RECT 46500.0 115950.0 45300.0 114750.0 ; + RECT 46500.0 115950.0 45300.0 114750.0 ; + RECT 48900.0 115950.0 47700.0 114750.0 ; + RECT 46500.0 115950.0 45300.0 114750.0 ; + RECT 44100.0 115950.0 42900.0 114750.0 ; + RECT 44100.0 115950.0 42900.0 114750.0 ; + RECT 46500.0 115950.0 45300.0 114750.0 ; + RECT 48900.0 124650.0 47700.0 123450.0 ; + RECT 46500.0 124650.0 45300.0 123450.0 ; + RECT 46500.0 124650.0 45300.0 123450.0 ; + RECT 48900.0 124650.0 47700.0 123450.0 ; + RECT 46500.0 124650.0 45300.0 123450.0 ; + RECT 44100.0 124650.0 42900.0 123450.0 ; + RECT 44100.0 124650.0 42900.0 123450.0 ; + RECT 46500.0 124650.0 45300.0 123450.0 ; + RECT 41700.0 115350.0 40500.0 114150.0 ; + RECT 41700.0 125250.0 40500.0 124050.0 ; + RECT 44100.0 122100.0 45300.0 120900.0 ; + RECT 47100.0 119400.0 48300.0 118200.0 ; + RECT 46500.0 115950.0 45300.0 114750.0 ; + RECT 44100.0 124650.0 42900.0 123450.0 ; + RECT 42900.0 119400.0 44100.0 118200.0 ; + RECT 48300.0 119400.0 47100.0 118200.0 ; + RECT 45300.0 122100.0 44100.0 120900.0 ; + RECT 44100.0 119400.0 42900.0 118200.0 ; + RECT 50700.0 113250.0 36300.0 112350.0 ; + RECT 50700.0 127050.0 36300.0 126150.0 ; + RECT 48900.0 128550.0 47700.0 126150.0 ; + RECT 48900.0 137250.0 47700.0 140850.0 ; + RECT 44100.0 137250.0 42900.0 140850.0 ; + RECT 41700.0 138450.0 40500.0 140400.0 ; + RECT 41700.0 126600.0 40500.0 128550.0 ; + RECT 48900.0 137250.0 47700.0 138450.0 ; + RECT 46500.0 137250.0 45300.0 138450.0 ; + RECT 46500.0 137250.0 45300.0 138450.0 ; + RECT 48900.0 137250.0 47700.0 138450.0 ; + RECT 46500.0 137250.0 45300.0 138450.0 ; + RECT 44100.0 137250.0 42900.0 138450.0 ; + RECT 44100.0 137250.0 42900.0 138450.0 ; + RECT 46500.0 137250.0 45300.0 138450.0 ; + RECT 48900.0 128550.0 47700.0 129750.0 ; + RECT 46500.0 128550.0 45300.0 129750.0 ; + RECT 46500.0 128550.0 45300.0 129750.0 ; + RECT 48900.0 128550.0 47700.0 129750.0 ; + RECT 46500.0 128550.0 45300.0 129750.0 ; + RECT 44100.0 128550.0 42900.0 129750.0 ; + RECT 44100.0 128550.0 42900.0 129750.0 ; + RECT 46500.0 128550.0 45300.0 129750.0 ; + RECT 41700.0 137850.0 40500.0 139050.0 ; + RECT 41700.0 127950.0 40500.0 129150.0 ; + RECT 44100.0 131100.0 45300.0 132300.0 ; + RECT 47100.0 133800.0 48300.0 135000.0 ; + RECT 46500.0 137250.0 45300.0 138450.0 ; + RECT 44100.0 128550.0 42900.0 129750.0 ; + RECT 42900.0 133800.0 44100.0 135000.0 ; + RECT 48300.0 133800.0 47100.0 135000.0 ; + RECT 45300.0 131100.0 44100.0 132300.0 ; + RECT 44100.0 133800.0 42900.0 135000.0 ; + RECT 50700.0 139950.0 36300.0 140850.0 ; + RECT 50700.0 126150.0 36300.0 127050.0 ; + RECT 48900.0 152250.0 47700.0 154650.0 ; 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47100.0 147000.0 48300.0 145800.0 ; + RECT 46500.0 143550.0 45300.0 142350.0 ; + RECT 44100.0 152250.0 42900.0 151050.0 ; + RECT 42900.0 147000.0 44100.0 145800.0 ; + RECT 48300.0 147000.0 47100.0 145800.0 ; + RECT 45300.0 149700.0 44100.0 148500.0 ; + RECT 44100.0 147000.0 42900.0 145800.0 ; + RECT 50700.0 140850.0 36300.0 139950.0 ; + RECT 50700.0 154650.0 36300.0 153750.0 ; + RECT 61650.0 109500.0 62850.0 110700.0 ; + RECT 80250.0 105000.0 81450.0 106200.0 ; + RECT 58650.0 123300.0 59850.0 124500.0 ; + RECT 77250.0 119400.0 78450.0 120600.0 ; + RECT 80250.0 128100.0 81450.0 129300.0 ; + RECT 55650.0 128100.0 56850.0 129300.0 ; + RECT 77250.0 141900.0 78450.0 143100.0 ; + RECT 52650.0 141900.0 53850.0 143100.0 ; + RECT 61650.0 106200.0 62850.0 107400.0 ; + RECT 58650.0 103500.0 59850.0 104700.0 ; + RECT 55650.0 118200.0 56850.0 119400.0 ; + RECT 58650.0 120900.0 59850.0 122100.0 ; + RECT 61650.0 133800.0 62850.0 135000.0 ; + RECT 52650.0 131100.0 53850.0 132300.0 ; + RECT 55650.0 145800.0 56850.0 147000.0 ; + RECT 52650.0 148500.0 53850.0 149700.0 ; + RECT 30450.0 105150.0 26700.0 106050.0 ; + RECT 30450.0 119550.0 26700.0 120450.0 ; + RECT 30450.0 132750.0 26700.0 133650.0 ; + RECT 30450.0 147150.0 26700.0 148050.0 ; + RECT 81300.0 112350.0 26700.0 113250.0 ; + RECT 81300.0 139950.0 26700.0 140850.0 ; + RECT 81300.0 98550.0 26700.0 99450.0 ; + RECT 81300.0 126150.0 26700.0 127050.0 ; + RECT 81300.0 153750.0 26700.0 154650.0 ; + RECT 65250.0 160350.0 64350.0 161250.0 ; + RECT 65250.0 164850.0 64350.0 165750.0 ; + RECT 69450.0 160350.0 64800.0 161250.0 ; + RECT 65250.0 160800.0 64350.0 165300.0 ; + RECT 64800.0 164850.0 62250.0 165750.0 ; + RECT 80850.0 160350.0 72900.0 161250.0 ; + RECT 65250.0 174750.0 64350.0 175650.0 ; + RECT 65250.0 178650.0 64350.0 179550.0 ; + RECT 69450.0 174750.0 64800.0 175650.0 ; + RECT 65250.0 175200.0 64350.0 179100.0 ; + RECT 64800.0 178650.0 59250.0 179550.0 ; + RECT 77850.0 174750.0 72900.0 175650.0 ; + RECT 80850.0 183450.0 56250.0 184350.0 ; + RECT 77850.0 197250.0 53250.0 198150.0 ; + RECT 62250.0 161550.0 48300.0 162450.0 ; + RECT 59250.0 158850.0 45300.0 159750.0 ; + RECT 56250.0 173550.0 48300.0 174450.0 ; + RECT 59250.0 176250.0 45300.0 177150.0 ; + RECT 62250.0 189150.0 48300.0 190050.0 ; + RECT 53250.0 186450.0 45300.0 187350.0 ; + RECT 56250.0 201150.0 48300.0 202050.0 ; + RECT 53250.0 203850.0 45300.0 204750.0 ; + RECT 38850.0 161550.0 37950.0 162450.0 ; + RECT 38850.0 160350.0 37950.0 161250.0 ; + RECT 42900.0 161550.0 38400.0 162450.0 ; + RECT 38850.0 160800.0 37950.0 162000.0 ; + RECT 38400.0 160350.0 33900.0 161250.0 ; + RECT 38850.0 173550.0 37950.0 174450.0 ; + RECT 38850.0 174750.0 37950.0 175650.0 ; + RECT 42900.0 173550.0 38400.0 174450.0 ; + RECT 38850.0 174000.0 37950.0 175200.0 ; + RECT 38400.0 174750.0 33900.0 175650.0 ; + RECT 38850.0 189150.0 37950.0 190050.0 ; + RECT 38850.0 187950.0 37950.0 188850.0 ; + RECT 42900.0 189150.0 38400.0 190050.0 ; + RECT 38850.0 188400.0 37950.0 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+ RECT 35700.0 238350.0 36900.0 239550.0 ; + RECT 33300.0 241500.0 32100.0 242700.0 ; + RECT 30300.0 244200.0 29100.0 245400.0 ; + RECT 30900.0 247650.0 32100.0 248850.0 ; + RECT 33300.0 238950.0 34500.0 240150.0 ; + RECT 34500.0 244200.0 33300.0 245400.0 ; + RECT 29100.0 244200.0 30300.0 245400.0 ; + RECT 32100.0 241500.0 33300.0 242700.0 ; + RECT 33300.0 244200.0 34500.0 245400.0 ; + RECT 26700.0 250350.0 41100.0 251250.0 ; + RECT 26700.0 236550.0 41100.0 237450.0 ; + RECT 28500.0 262650.0 29700.0 265050.0 ; + RECT 28500.0 253950.0 29700.0 250350.0 ; + RECT 33300.0 253950.0 34500.0 250350.0 ; + RECT 35700.0 252750.0 36900.0 250800.0 ; + RECT 35700.0 264600.0 36900.0 262650.0 ; + RECT 28500.0 253950.0 29700.0 252750.0 ; + RECT 30900.0 253950.0 32100.0 252750.0 ; + RECT 30900.0 253950.0 32100.0 252750.0 ; + RECT 28500.0 253950.0 29700.0 252750.0 ; + RECT 30900.0 253950.0 32100.0 252750.0 ; + RECT 33300.0 253950.0 34500.0 252750.0 ; + RECT 33300.0 253950.0 34500.0 252750.0 ; + RECT 30900.0 253950.0 32100.0 252750.0 ; + RECT 28500.0 262650.0 29700.0 261450.0 ; + RECT 30900.0 262650.0 32100.0 261450.0 ; + RECT 30900.0 262650.0 32100.0 261450.0 ; + RECT 28500.0 262650.0 29700.0 261450.0 ; + RECT 30900.0 262650.0 32100.0 261450.0 ; + RECT 33300.0 262650.0 34500.0 261450.0 ; + RECT 33300.0 262650.0 34500.0 261450.0 ; + RECT 30900.0 262650.0 32100.0 261450.0 ; + RECT 35700.0 253350.0 36900.0 252150.0 ; + RECT 35700.0 263250.0 36900.0 262050.0 ; + RECT 33300.0 260100.0 32100.0 258900.0 ; + RECT 30300.0 257400.0 29100.0 256200.0 ; + RECT 30900.0 253950.0 32100.0 252750.0 ; + RECT 33300.0 262650.0 34500.0 261450.0 ; + RECT 34500.0 257400.0 33300.0 256200.0 ; + RECT 29100.0 257400.0 30300.0 256200.0 ; + RECT 32100.0 260100.0 33300.0 258900.0 ; + RECT 33300.0 257400.0 34500.0 256200.0 ; + RECT 26700.0 251250.0 41100.0 250350.0 ; + RECT 26700.0 265050.0 41100.0 264150.0 ; + RECT 28500.0 266550.0 29700.0 264150.0 ; + RECT 28500.0 275250.0 29700.0 278850.0 ; + RECT 33300.0 275250.0 34500.0 278850.0 ; + RECT 35700.0 276450.0 36900.0 278400.0 ; + RECT 35700.0 264600.0 36900.0 266550.0 ; + RECT 28500.0 275250.0 29700.0 276450.0 ; + RECT 30900.0 275250.0 32100.0 276450.0 ; + RECT 30900.0 275250.0 32100.0 276450.0 ; + RECT 28500.0 275250.0 29700.0 276450.0 ; + RECT 30900.0 275250.0 32100.0 276450.0 ; + RECT 33300.0 275250.0 34500.0 276450.0 ; + RECT 33300.0 275250.0 34500.0 276450.0 ; + RECT 30900.0 275250.0 32100.0 276450.0 ; + RECT 28500.0 266550.0 29700.0 267750.0 ; + RECT 30900.0 266550.0 32100.0 267750.0 ; + RECT 30900.0 266550.0 32100.0 267750.0 ; + RECT 28500.0 266550.0 29700.0 267750.0 ; + RECT 30900.0 266550.0 32100.0 267750.0 ; + RECT 33300.0 266550.0 34500.0 267750.0 ; + RECT 33300.0 266550.0 34500.0 267750.0 ; + RECT 30900.0 266550.0 32100.0 267750.0 ; + RECT 35700.0 275850.0 36900.0 277050.0 ; + RECT 35700.0 265950.0 36900.0 267150.0 ; + RECT 33300.0 269100.0 32100.0 270300.0 ; + RECT 30300.0 271800.0 29100.0 273000.0 ; + RECT 30900.0 275250.0 32100.0 276450.0 ; + RECT 33300.0 266550.0 34500.0 267750.0 ; + RECT 34500.0 271800.0 33300.0 273000.0 ; + RECT 29100.0 271800.0 30300.0 273000.0 ; + RECT 32100.0 269100.0 33300.0 270300.0 ; + RECT 33300.0 271800.0 34500.0 273000.0 ; + RECT 26700.0 277950.0 41100.0 278850.0 ; + RECT 26700.0 264150.0 41100.0 265050.0 ; + RECT 28500.0 290250.0 29700.0 292650.0 ; + RECT 28500.0 281550.0 29700.0 277950.0 ; + RECT 33300.0 281550.0 34500.0 277950.0 ; + RECT 35700.0 280350.0 36900.0 278400.0 ; + RECT 35700.0 292200.0 36900.0 290250.0 ; + RECT 28500.0 281550.0 29700.0 280350.0 ; + RECT 30900.0 281550.0 32100.0 280350.0 ; + RECT 30900.0 281550.0 32100.0 280350.0 ; + RECT 28500.0 281550.0 29700.0 280350.0 ; + RECT 30900.0 281550.0 32100.0 280350.0 ; + RECT 33300.0 281550.0 34500.0 280350.0 ; + RECT 33300.0 281550.0 34500.0 280350.0 ; + RECT 30900.0 281550.0 32100.0 280350.0 ; + RECT 28500.0 290250.0 29700.0 289050.0 ; + RECT 30900.0 290250.0 32100.0 289050.0 ; + RECT 30900.0 290250.0 32100.0 289050.0 ; + RECT 28500.0 290250.0 29700.0 289050.0 ; + RECT 30900.0 290250.0 32100.0 289050.0 ; + RECT 33300.0 290250.0 34500.0 289050.0 ; + RECT 33300.0 290250.0 34500.0 289050.0 ; + RECT 30900.0 290250.0 32100.0 289050.0 ; + RECT 35700.0 280950.0 36900.0 279750.0 ; + RECT 35700.0 290850.0 36900.0 289650.0 ; + RECT 33300.0 287700.0 32100.0 286500.0 ; + RECT 30300.0 285000.0 29100.0 283800.0 ; + RECT 30900.0 281550.0 32100.0 280350.0 ; + RECT 33300.0 290250.0 34500.0 289050.0 ; + RECT 34500.0 285000.0 33300.0 283800.0 ; + RECT 29100.0 285000.0 30300.0 283800.0 ; + RECT 32100.0 287700.0 33300.0 286500.0 ; + RECT 33300.0 285000.0 34500.0 283800.0 ; + RECT 26700.0 278850.0 41100.0 277950.0 ; + RECT 26700.0 292650.0 41100.0 291750.0 ; + RECT 28500.0 294150.0 29700.0 291750.0 ; + RECT 28500.0 302850.0 29700.0 306450.0 ; + RECT 33300.0 302850.0 34500.0 306450.0 ; + RECT 35700.0 304050.0 36900.0 306000.0 ; + RECT 35700.0 292200.0 36900.0 294150.0 ; + RECT 28500.0 302850.0 29700.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 28500.0 302850.0 29700.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 33300.0 302850.0 34500.0 304050.0 ; + RECT 33300.0 302850.0 34500.0 304050.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 28500.0 294150.0 29700.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 28500.0 294150.0 29700.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 33300.0 294150.0 34500.0 295350.0 ; + RECT 33300.0 294150.0 34500.0 295350.0 ; + RECT 30900.0 294150.0 32100.0 295350.0 ; + RECT 35700.0 303450.0 36900.0 304650.0 ; + RECT 35700.0 293550.0 36900.0 294750.0 ; + RECT 33300.0 296700.0 32100.0 297900.0 ; + RECT 30300.0 299400.0 29100.0 300600.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 33300.0 294150.0 34500.0 295350.0 ; + RECT 34500.0 299400.0 33300.0 300600.0 ; + RECT 29100.0 299400.0 30300.0 300600.0 ; + RECT 32100.0 296700.0 33300.0 297900.0 ; + RECT 33300.0 299400.0 34500.0 300600.0 ; + RECT 26700.0 305550.0 41100.0 306450.0 ; + RECT 26700.0 291750.0 41100.0 292650.0 ; + RECT 28500.0 317850.0 29700.0 320250.0 ; + RECT 28500.0 309150.0 29700.0 305550.0 ; + RECT 33300.0 309150.0 34500.0 305550.0 ; + RECT 35700.0 307950.0 36900.0 306000.0 ; + RECT 35700.0 319800.0 36900.0 317850.0 ; + RECT 28500.0 309150.0 29700.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 28500.0 309150.0 29700.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 33300.0 309150.0 34500.0 307950.0 ; + RECT 33300.0 309150.0 34500.0 307950.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 28500.0 317850.0 29700.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 28500.0 317850.0 29700.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 33300.0 317850.0 34500.0 316650.0 ; + RECT 33300.0 317850.0 34500.0 316650.0 ; + RECT 30900.0 317850.0 32100.0 316650.0 ; + RECT 35700.0 308550.0 36900.0 307350.0 ; + RECT 35700.0 318450.0 36900.0 317250.0 ; + RECT 33300.0 315300.0 32100.0 314100.0 ; + RECT 30300.0 312600.0 29100.0 311400.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 33300.0 317850.0 34500.0 316650.0 ; + RECT 34500.0 312600.0 33300.0 311400.0 ; + RECT 29100.0 312600.0 30300.0 311400.0 ; + RECT 32100.0 315300.0 33300.0 314100.0 ; + RECT 33300.0 312600.0 34500.0 311400.0 ; + RECT 26700.0 306450.0 41100.0 305550.0 ; + RECT 26700.0 320250.0 41100.0 319350.0 ; + RECT 28500.0 321750.0 29700.0 319350.0 ; + RECT 28500.0 330450.0 29700.0 334050.0 ; + RECT 33300.0 330450.0 34500.0 334050.0 ; + RECT 35700.0 331650.0 36900.0 333600.0 ; + RECT 35700.0 319800.0 36900.0 321750.0 ; + RECT 28500.0 330450.0 29700.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 28500.0 330450.0 29700.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 33300.0 330450.0 34500.0 331650.0 ; + RECT 33300.0 330450.0 34500.0 331650.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 28500.0 321750.0 29700.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 28500.0 321750.0 29700.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 33300.0 321750.0 34500.0 322950.0 ; + RECT 33300.0 321750.0 34500.0 322950.0 ; + RECT 30900.0 321750.0 32100.0 322950.0 ; + RECT 35700.0 331050.0 36900.0 332250.0 ; + RECT 35700.0 321150.0 36900.0 322350.0 ; + RECT 33300.0 324300.0 32100.0 325500.0 ; + RECT 30300.0 327000.0 29100.0 328200.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 33300.0 321750.0 34500.0 322950.0 ; + RECT 34500.0 327000.0 33300.0 328200.0 ; + RECT 29100.0 327000.0 30300.0 328200.0 ; + RECT 32100.0 324300.0 33300.0 325500.0 ; + RECT 33300.0 327000.0 34500.0 328200.0 ; + RECT 26700.0 333150.0 41100.0 334050.0 ; + RECT 26700.0 319350.0 41100.0 320250.0 ; + RECT 28500.0 345450.0 29700.0 347850.0 ; + RECT 28500.0 336750.0 29700.0 333150.0 ; + RECT 33300.0 336750.0 34500.0 333150.0 ; + RECT 35700.0 335550.0 36900.0 333600.0 ; + RECT 35700.0 347400.0 36900.0 345450.0 ; + RECT 28500.0 336750.0 29700.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 28500.0 336750.0 29700.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 33300.0 336750.0 34500.0 335550.0 ; + RECT 33300.0 336750.0 34500.0 335550.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 28500.0 345450.0 29700.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 28500.0 345450.0 29700.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 33300.0 345450.0 34500.0 344250.0 ; + RECT 33300.0 345450.0 34500.0 344250.0 ; + RECT 30900.0 345450.0 32100.0 344250.0 ; + RECT 35700.0 336150.0 36900.0 334950.0 ; + RECT 35700.0 346050.0 36900.0 344850.0 ; + RECT 33300.0 342900.0 32100.0 341700.0 ; + RECT 30300.0 340200.0 29100.0 339000.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 33300.0 345450.0 34500.0 344250.0 ; + RECT 34500.0 340200.0 33300.0 339000.0 ; + RECT 29100.0 340200.0 30300.0 339000.0 ; + RECT 32100.0 342900.0 33300.0 341700.0 ; + RECT 33300.0 340200.0 34500.0 339000.0 ; + RECT 26700.0 334050.0 41100.0 333150.0 ; + RECT 26700.0 347850.0 41100.0 346950.0 ; + RECT 28500.0 349350.0 29700.0 346950.0 ; + RECT 28500.0 358050.0 29700.0 361650.0 ; + RECT 33300.0 358050.0 34500.0 361650.0 ; + RECT 35700.0 359250.0 36900.0 361200.0 ; + RECT 35700.0 347400.0 36900.0 349350.0 ; + RECT 28500.0 358050.0 29700.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 28500.0 358050.0 29700.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 33300.0 358050.0 34500.0 359250.0 ; + RECT 33300.0 358050.0 34500.0 359250.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 28500.0 349350.0 29700.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 28500.0 349350.0 29700.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 33300.0 349350.0 34500.0 350550.0 ; + RECT 33300.0 349350.0 34500.0 350550.0 ; + RECT 30900.0 349350.0 32100.0 350550.0 ; + RECT 35700.0 358650.0 36900.0 359850.0 ; + RECT 35700.0 348750.0 36900.0 349950.0 ; + RECT 33300.0 351900.0 32100.0 353100.0 ; + RECT 30300.0 354600.0 29100.0 355800.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 33300.0 349350.0 34500.0 350550.0 ; + RECT 34500.0 354600.0 33300.0 355800.0 ; + RECT 29100.0 354600.0 30300.0 355800.0 ; + RECT 32100.0 351900.0 33300.0 353100.0 ; + RECT 33300.0 354600.0 34500.0 355800.0 ; + RECT 26700.0 360750.0 41100.0 361650.0 ; + RECT 26700.0 346950.0 41100.0 347850.0 ; + RECT 28500.0 373050.0 29700.0 375450.0 ; + RECT 28500.0 364350.0 29700.0 360750.0 ; + RECT 33300.0 364350.0 34500.0 360750.0 ; + RECT 35700.0 363150.0 36900.0 361200.0 ; + RECT 35700.0 375000.0 36900.0 373050.0 ; + RECT 28500.0 364350.0 29700.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 28500.0 364350.0 29700.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 33300.0 364350.0 34500.0 363150.0 ; + RECT 33300.0 364350.0 34500.0 363150.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 28500.0 373050.0 29700.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 28500.0 373050.0 29700.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 33300.0 373050.0 34500.0 371850.0 ; + RECT 33300.0 373050.0 34500.0 371850.0 ; + RECT 30900.0 373050.0 32100.0 371850.0 ; + RECT 35700.0 363750.0 36900.0 362550.0 ; + RECT 35700.0 373650.0 36900.0 372450.0 ; + RECT 33300.0 370500.0 32100.0 369300.0 ; + RECT 30300.0 367800.0 29100.0 366600.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 33300.0 373050.0 34500.0 371850.0 ; + RECT 34500.0 367800.0 33300.0 366600.0 ; + RECT 29100.0 367800.0 30300.0 366600.0 ; + RECT 32100.0 370500.0 33300.0 369300.0 ; + RECT 33300.0 367800.0 34500.0 366600.0 ; + RECT 26700.0 361650.0 41100.0 360750.0 ; + RECT 26700.0 375450.0 41100.0 374550.0 ; + RECT 28500.0 376950.0 29700.0 374550.0 ; + RECT 28500.0 385650.0 29700.0 389250.0 ; + RECT 33300.0 385650.0 34500.0 389250.0 ; + RECT 35700.0 386850.0 36900.0 388800.0 ; + RECT 35700.0 375000.0 36900.0 376950.0 ; + RECT 28500.0 385650.0 29700.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 28500.0 385650.0 29700.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 33300.0 385650.0 34500.0 386850.0 ; + RECT 33300.0 385650.0 34500.0 386850.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 28500.0 376950.0 29700.0 378150.0 ; + RECT 30900.0 376950.0 32100.0 378150.0 ; + RECT 30900.0 376950.0 32100.0 378150.0 ; + RECT 28500.0 376950.0 29700.0 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33300.0 395400.0 34500.0 394200.0 ; + RECT 26700.0 389250.0 41100.0 388350.0 ; + RECT 26700.0 403050.0 41100.0 402150.0 ; + RECT 28500.0 404550.0 29700.0 402150.0 ; + RECT 28500.0 413250.0 29700.0 416850.0 ; + RECT 33300.0 413250.0 34500.0 416850.0 ; + RECT 35700.0 414450.0 36900.0 416400.0 ; + RECT 35700.0 402600.0 36900.0 404550.0 ; + RECT 28500.0 413250.0 29700.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 28500.0 413250.0 29700.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 33300.0 413250.0 34500.0 414450.0 ; + RECT 33300.0 413250.0 34500.0 414450.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 28500.0 404550.0 29700.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 28500.0 404550.0 29700.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 33300.0 404550.0 34500.0 405750.0 ; + RECT 33300.0 404550.0 34500.0 405750.0 ; + RECT 30900.0 404550.0 32100.0 405750.0 ; + RECT 35700.0 413850.0 36900.0 415050.0 ; + RECT 35700.0 403950.0 36900.0 405150.0 ; + RECT 33300.0 407100.0 32100.0 408300.0 ; + RECT 30300.0 409800.0 29100.0 411000.0 ; + RECT 30900.0 413250.0 32100.0 414450.0 ; + RECT 33300.0 404550.0 34500.0 405750.0 ; + RECT 34500.0 409800.0 33300.0 411000.0 ; + RECT 29100.0 409800.0 30300.0 411000.0 ; + RECT 32100.0 407100.0 33300.0 408300.0 ; + RECT 33300.0 409800.0 34500.0 411000.0 ; + RECT 26700.0 415950.0 41100.0 416850.0 ; + RECT 26700.0 402150.0 41100.0 403050.0 ; + RECT 28500.0 428250.0 29700.0 430650.0 ; + RECT 28500.0 419550.0 29700.0 415950.0 ; + RECT 33300.0 419550.0 34500.0 415950.0 ; + RECT 35700.0 418350.0 36900.0 416400.0 ; + RECT 35700.0 430200.0 36900.0 428250.0 ; + RECT 28500.0 419550.0 29700.0 418350.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 28500.0 419550.0 29700.0 418350.0 ; + RECT 30900.0 419550.0 32100.0 418350.0 ; + RECT 33300.0 419550.0 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223200.0 ; + RECT 47700.0 209400.0 48900.0 211350.0 ; + RECT 42900.0 210750.0 44100.0 208950.0 ; + RECT 42900.0 220050.0 44100.0 223650.0 ; + RECT 45600.0 210750.0 46500.0 220050.0 ; + RECT 42900.0 220050.0 44100.0 221250.0 ; + RECT 45300.0 220050.0 46500.0 221250.0 ; + RECT 45300.0 220050.0 46500.0 221250.0 ; + RECT 42900.0 220050.0 44100.0 221250.0 ; + RECT 42900.0 210750.0 44100.0 211950.0 ; + RECT 45300.0 210750.0 46500.0 211950.0 ; + RECT 45300.0 210750.0 46500.0 211950.0 ; + RECT 42900.0 210750.0 44100.0 211950.0 ; + RECT 47700.0 220650.0 48900.0 221850.0 ; + RECT 47700.0 210750.0 48900.0 211950.0 ; + RECT 43500.0 215400.0 44700.0 216600.0 ; + RECT 43500.0 215400.0 44700.0 216600.0 ; + RECT 46050.0 215550.0 46950.0 216450.0 ; + RECT 41100.0 222750.0 50700.0 223650.0 ; + RECT 41100.0 208950.0 50700.0 209850.0 ; + RECT 47700.0 225150.0 48900.0 223200.0 ; + RECT 47700.0 237000.0 48900.0 235050.0 ; + RECT 42900.0 235650.0 44100.0 237450.0 ; + RECT 42900.0 226350.0 44100.0 222750.0 ; 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RECT 78450.0 229950.0 79350.0 230850.0 ; + RECT 74400.0 228750.0 78900.0 229650.0 ; + RECT 78450.0 229200.0 79350.0 230400.0 ; + RECT 78900.0 229950.0 83400.0 230850.0 ; + RECT 53850.0 243150.0 59400.0 244050.0 ; + RECT 61950.0 244350.0 62850.0 245250.0 ; + RECT 61950.0 243150.0 62850.0 244050.0 ; + RECT 61950.0 244050.0 62850.0 244800.0 ; + RECT 62400.0 244350.0 69000.0 245250.0 ; + RECT 69000.0 244350.0 70200.0 245250.0 ; + RECT 78450.0 244350.0 79350.0 245250.0 ; + RECT 78450.0 243150.0 79350.0 244050.0 ; + RECT 74400.0 244350.0 78900.0 245250.0 ; + RECT 78450.0 243600.0 79350.0 244800.0 ; + RECT 78900.0 243150.0 83400.0 244050.0 ; + RECT 53850.0 257550.0 59400.0 258450.0 ; + RECT 61950.0 256350.0 62850.0 257250.0 ; + RECT 61950.0 257550.0 62850.0 258450.0 ; + RECT 61950.0 256800.0 62850.0 258450.0 ; + RECT 62400.0 256350.0 69000.0 257250.0 ; + RECT 69000.0 256350.0 70200.0 257250.0 ; + RECT 78450.0 256350.0 79350.0 257250.0 ; + RECT 78450.0 257550.0 79350.0 258450.0 ; + RECT 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68400.0 226350.0 69600.0 222750.0 ; + RECT 73200.0 226350.0 74400.0 222750.0 ; + RECT 75600.0 225150.0 76800.0 223200.0 ; + RECT 75600.0 237000.0 76800.0 235050.0 ; + RECT 68400.0 226350.0 69600.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 68400.0 226350.0 69600.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 73200.0 226350.0 74400.0 225150.0 ; + RECT 73200.0 226350.0 74400.0 225150.0 ; + RECT 70800.0 226350.0 72000.0 225150.0 ; + RECT 68400.0 235050.0 69600.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 68400.0 235050.0 69600.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 73200.0 235050.0 74400.0 233850.0 ; + RECT 73200.0 235050.0 74400.0 233850.0 ; + RECT 70800.0 235050.0 72000.0 233850.0 ; + RECT 75600.0 225750.0 76800.0 224550.0 ; + RECT 75600.0 235650.0 76800.0 234450.0 ; + RECT 73200.0 232500.0 72000.0 231300.0 ; + RECT 70200.0 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68400.0 275250.0 69600.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 68400.0 275250.0 69600.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 73200.0 275250.0 74400.0 276450.0 ; + RECT 73200.0 275250.0 74400.0 276450.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 68400.0 266550.0 69600.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 68400.0 266550.0 69600.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 70800.0 266550.0 72000.0 267750.0 ; + RECT 75600.0 275850.0 76800.0 277050.0 ; + RECT 75600.0 265950.0 76800.0 267150.0 ; + RECT 73200.0 269100.0 72000.0 270300.0 ; + RECT 70200.0 271800.0 69000.0 273000.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 74400.0 271800.0 73200.0 273000.0 ; + RECT 69000.0 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90600.0 278850.0 ; + RECT 81000.0 264150.0 90600.0 265050.0 ; + RECT 53250.0 270600.0 54450.0 271800.0 ; + RECT 55200.0 268200.0 56400.0 269400.0 ; + RECT 72000.0 269100.0 70800.0 270300.0 ; + RECT 63600.0 280350.0 64800.0 278400.0 ; + RECT 63600.0 292200.0 64800.0 290250.0 ; + RECT 58800.0 290850.0 60000.0 292650.0 ; + RECT 58800.0 281550.0 60000.0 277950.0 ; + RECT 61500.0 290850.0 62400.0 281550.0 ; + RECT 58800.0 281550.0 60000.0 280350.0 ; + RECT 61200.0 281550.0 62400.0 280350.0 ; + RECT 61200.0 281550.0 62400.0 280350.0 ; + RECT 58800.0 281550.0 60000.0 280350.0 ; + RECT 58800.0 290850.0 60000.0 289650.0 ; + RECT 61200.0 290850.0 62400.0 289650.0 ; + RECT 61200.0 290850.0 62400.0 289650.0 ; + RECT 58800.0 290850.0 60000.0 289650.0 ; + RECT 63600.0 280950.0 64800.0 279750.0 ; + RECT 63600.0 290850.0 64800.0 289650.0 ; + RECT 59400.0 286200.0 60600.0 285000.0 ; + RECT 59400.0 286200.0 60600.0 285000.0 ; + RECT 61950.0 286050.0 62850.0 285150.0 ; + RECT 57000.0 278850.0 66600.0 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82800.0 290850.0 84000.0 289650.0 ; + RECT 87600.0 280950.0 88800.0 279750.0 ; + RECT 87600.0 290850.0 88800.0 289650.0 ; + RECT 83400.0 286200.0 84600.0 285000.0 ; + RECT 83400.0 286200.0 84600.0 285000.0 ; + RECT 85950.0 286050.0 86850.0 285150.0 ; + RECT 81000.0 278850.0 90600.0 277950.0 ; + RECT 81000.0 292650.0 90600.0 291750.0 ; + RECT 53250.0 285000.0 54450.0 286200.0 ; + RECT 55200.0 287400.0 56400.0 288600.0 ; + RECT 72000.0 286500.0 70800.0 287700.0 ; + RECT 63600.0 304050.0 64800.0 306000.0 ; + RECT 63600.0 292200.0 64800.0 294150.0 ; + RECT 58800.0 293550.0 60000.0 291750.0 ; + RECT 58800.0 302850.0 60000.0 306450.0 ; + RECT 61500.0 293550.0 62400.0 302850.0 ; + RECT 58800.0 302850.0 60000.0 304050.0 ; + RECT 61200.0 302850.0 62400.0 304050.0 ; + RECT 61200.0 302850.0 62400.0 304050.0 ; + RECT 58800.0 302850.0 60000.0 304050.0 ; + RECT 58800.0 293550.0 60000.0 294750.0 ; + RECT 61200.0 293550.0 62400.0 294750.0 ; + RECT 61200.0 293550.0 62400.0 294750.0 ; + RECT 58800.0 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83400.0 325800.0 84600.0 327000.0 ; + RECT 85950.0 325950.0 86850.0 326850.0 ; + RECT 81000.0 333150.0 90600.0 334050.0 ; + RECT 81000.0 319350.0 90600.0 320250.0 ; + RECT 53250.0 325800.0 54450.0 327000.0 ; + RECT 55200.0 323400.0 56400.0 324600.0 ; + RECT 72000.0 324300.0 70800.0 325500.0 ; + RECT 63600.0 335550.0 64800.0 333600.0 ; + RECT 63600.0 347400.0 64800.0 345450.0 ; + RECT 58800.0 346050.0 60000.0 347850.0 ; + RECT 58800.0 336750.0 60000.0 333150.0 ; + RECT 61500.0 346050.0 62400.0 336750.0 ; + RECT 58800.0 336750.0 60000.0 335550.0 ; + RECT 61200.0 336750.0 62400.0 335550.0 ; + RECT 61200.0 336750.0 62400.0 335550.0 ; + RECT 58800.0 336750.0 60000.0 335550.0 ; + RECT 58800.0 346050.0 60000.0 344850.0 ; + RECT 61200.0 346050.0 62400.0 344850.0 ; + RECT 61200.0 346050.0 62400.0 344850.0 ; + RECT 58800.0 346050.0 60000.0 344850.0 ; + RECT 63600.0 336150.0 64800.0 334950.0 ; + RECT 63600.0 346050.0 64800.0 344850.0 ; + RECT 59400.0 341400.0 60600.0 340200.0 ; + RECT 59400.0 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376950.0 69600.0 374550.0 ; + RECT 68400.0 385650.0 69600.0 389250.0 ; + RECT 73200.0 385650.0 74400.0 389250.0 ; + RECT 75600.0 386850.0 76800.0 388800.0 ; + RECT 75600.0 375000.0 76800.0 376950.0 ; + RECT 68400.0 385650.0 69600.0 386850.0 ; + RECT 70800.0 385650.0 72000.0 386850.0 ; + RECT 70800.0 385650.0 72000.0 386850.0 ; + RECT 68400.0 385650.0 69600.0 386850.0 ; + RECT 70800.0 385650.0 72000.0 386850.0 ; + RECT 73200.0 385650.0 74400.0 386850.0 ; + RECT 73200.0 385650.0 74400.0 386850.0 ; + RECT 70800.0 385650.0 72000.0 386850.0 ; + RECT 68400.0 376950.0 69600.0 378150.0 ; + RECT 70800.0 376950.0 72000.0 378150.0 ; + RECT 70800.0 376950.0 72000.0 378150.0 ; + RECT 68400.0 376950.0 69600.0 378150.0 ; + RECT 70800.0 376950.0 72000.0 378150.0 ; + RECT 73200.0 376950.0 74400.0 378150.0 ; + RECT 73200.0 376950.0 74400.0 378150.0 ; + RECT 70800.0 376950.0 72000.0 378150.0 ; + RECT 75600.0 386250.0 76800.0 387450.0 ; + RECT 75600.0 376350.0 76800.0 377550.0 ; + RECT 73200.0 379500.0 72000.0 380700.0 ; + RECT 70200.0 382200.0 69000.0 383400.0 ; + RECT 70800.0 385650.0 72000.0 386850.0 ; + RECT 73200.0 376950.0 74400.0 378150.0 ; + RECT 74400.0 382200.0 73200.0 383400.0 ; + RECT 69000.0 382200.0 70200.0 383400.0 ; + RECT 72000.0 379500.0 73200.0 380700.0 ; + RECT 73200.0 382200.0 74400.0 383400.0 ; + RECT 66600.0 388350.0 81000.0 389250.0 ; + RECT 66600.0 374550.0 81000.0 375450.0 ; + RECT 87600.0 386850.0 88800.0 388800.0 ; + RECT 87600.0 375000.0 88800.0 376950.0 ; + RECT 82800.0 376350.0 84000.0 374550.0 ; + RECT 82800.0 385650.0 84000.0 389250.0 ; + RECT 85500.0 376350.0 86400.0 385650.0 ; + RECT 82800.0 385650.0 84000.0 386850.0 ; + RECT 85200.0 385650.0 86400.0 386850.0 ; + RECT 85200.0 385650.0 86400.0 386850.0 ; + RECT 82800.0 385650.0 84000.0 386850.0 ; + RECT 82800.0 376350.0 84000.0 377550.0 ; + RECT 85200.0 376350.0 86400.0 377550.0 ; + RECT 85200.0 376350.0 86400.0 377550.0 ; + RECT 82800.0 376350.0 84000.0 377550.0 ; + RECT 87600.0 386250.0 88800.0 387450.0 ; + RECT 87600.0 376350.0 88800.0 377550.0 ; + RECT 83400.0 381000.0 84600.0 382200.0 ; + RECT 83400.0 381000.0 84600.0 382200.0 ; + RECT 85950.0 381150.0 86850.0 382050.0 ; + RECT 81000.0 388350.0 90600.0 389250.0 ; + RECT 81000.0 374550.0 90600.0 375450.0 ; + RECT 53250.0 381000.0 54450.0 382200.0 ; + RECT 55200.0 378600.0 56400.0 379800.0 ; + RECT 72000.0 379500.0 70800.0 380700.0 ; + RECT 63600.0 390750.0 64800.0 388800.0 ; + RECT 63600.0 402600.0 64800.0 400650.0 ; + RECT 58800.0 401250.0 60000.0 403050.0 ; + RECT 58800.0 391950.0 60000.0 388350.0 ; + RECT 61500.0 401250.0 62400.0 391950.0 ; + RECT 58800.0 391950.0 60000.0 390750.0 ; + RECT 61200.0 391950.0 62400.0 390750.0 ; + RECT 61200.0 391950.0 62400.0 390750.0 ; + RECT 58800.0 391950.0 60000.0 390750.0 ; + RECT 58800.0 401250.0 60000.0 400050.0 ; + RECT 61200.0 401250.0 62400.0 400050.0 ; + RECT 61200.0 401250.0 62400.0 400050.0 ; + RECT 58800.0 401250.0 60000.0 400050.0 ; + RECT 63600.0 391350.0 64800.0 390150.0 ; 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70800.0 400650.0 72000.0 399450.0 ; + RECT 73200.0 400650.0 74400.0 399450.0 ; + RECT 73200.0 400650.0 74400.0 399450.0 ; + RECT 70800.0 400650.0 72000.0 399450.0 ; + RECT 75600.0 391350.0 76800.0 390150.0 ; + RECT 75600.0 401250.0 76800.0 400050.0 ; + RECT 73200.0 398100.0 72000.0 396900.0 ; + RECT 70200.0 395400.0 69000.0 394200.0 ; + RECT 70800.0 391950.0 72000.0 390750.0 ; + RECT 73200.0 400650.0 74400.0 399450.0 ; + RECT 74400.0 395400.0 73200.0 394200.0 ; + RECT 69000.0 395400.0 70200.0 394200.0 ; + RECT 72000.0 398100.0 73200.0 396900.0 ; + RECT 73200.0 395400.0 74400.0 394200.0 ; + RECT 66600.0 389250.0 81000.0 388350.0 ; + RECT 66600.0 403050.0 81000.0 402150.0 ; + RECT 87600.0 390750.0 88800.0 388800.0 ; + RECT 87600.0 402600.0 88800.0 400650.0 ; + RECT 82800.0 401250.0 84000.0 403050.0 ; + RECT 82800.0 391950.0 84000.0 388350.0 ; + RECT 85500.0 401250.0 86400.0 391950.0 ; + RECT 82800.0 391950.0 84000.0 390750.0 ; + RECT 85200.0 391950.0 86400.0 390750.0 ; + RECT 85200.0 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RECT -35400.0 387900.0 -46800.0 388800.0 ; + RECT -35400.0 415500.0 -46800.0 416400.0 ; + RECT -30450.0 376200.0 -31650.0 377400.0 ; + RECT -30450.0 399600.0 -31650.0 400800.0 ; + RECT -30450.0 403800.0 -31650.0 405000.0 ; + RECT -30450.0 427200.0 -31650.0 428400.0 ; + RECT -30600.0 389700.0 -31800.0 390900.0 ; + RECT -30000.0 350100.0 -31200.0 351300.0 ; + RECT -36600.0 350700.0 -35400.0 351900.0 ; + RECT -46800.0 350700.0 -45600.0 351900.0 ; + RECT -23400.0 376500.0 -24600.0 377700.0 ; + RECT -33450.0 363000.0 -32250.0 364200.0 ; + RECT -33450.0 354900.0 -32250.0 356100.0 ; + RECT -40200.0 354900.0 -39000.0 356100.0 ; + RECT -9000.0 341700.0 -9900.0 392100.0 ; + RECT -23550.0 341700.0 -24450.0 355050.0 ; + RECT -48300.0 341700.0 -49200.0 432150.0 ; + RECT -16350.0 341700.0 -17250.0 389700.0 ; + RECT -30150.0 341700.0 -31050.0 351300.0 ; + RECT -2550.0 341700.0 -3450.0 389700.0 ; + RECT -8850.0 265050.0 -10050.0 263850.0 ; + RECT -8850.0 224100.0 -10050.0 222900.0 ; + RECT -18900.0 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319800.0 110550.0 322500.0 ; + RECT 106950.0 339600.0 107850.0 342300.0 ; + RECT 101550.0 300000.0 102450.0 302700.0 ; + RECT 98850.0 317100.0 99750.0 319800.0 ; + RECT 104250.0 280650.0 105150.0 283350.0 ; + RECT 96150.0 261750.0 97050.0 264450.0 ; + RECT 6300.0 275250.0 7200.0 277950.0 ; + RECT -3000.0 266700.0 1800.0 267600.0 ; + RECT 96150.0 0.0 97050.0 461850.0 ; + RECT 98850.0 0.0 99750.0 461850.0 ; + RECT 101550.0 0.0 102450.0 461850.0 ; + RECT 104250.0 0.0 105150.0 461850.0 ; + RECT 106950.0 0.0 107850.0 461850.0 ; + RECT 109650.0 0.0 110550.0 461850.0 ; + RECT 85350.0 47400.0 86250.0 209400.0 ; + RECT 88050.0 47400.0 88950.0 209400.0 ; + RECT 90750.0 47400.0 91650.0 209400.0 ; + RECT 93450.0 47400.0 94350.0 209400.0 ; + RECT 122550.0 432600.0 123450.0 433800.0 ; + RECT 132750.0 432600.0 133650.0 433800.0 ; + RECT 121050.0 15750.0 121950.0 16650.0 ; + RECT 117900.0 15750.0 121500.0 16650.0 ; + RECT 121050.0 16200.0 121950.0 18000.0 ; + RECT 131250.0 15750.0 132150.0 16650.0 ; + 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31500.0 284850.0 33900.0 283950.0 ; + RECT 33450.0 289050.0 34350.0 284400.0 ; + RECT 30900.0 281550.0 32100.0 280350.0 ; + RECT 33300.0 290250.0 34500.0 289050.0 ; + RECT 34500.0 285000.0 33300.0 283800.0 ; + RECT 31050.0 299550.0 31950.0 300450.0 ; + RECT 33450.0 299550.0 34350.0 300450.0 ; + RECT 31050.0 300000.0 31950.0 302850.0 ; + RECT 31500.0 299550.0 33900.0 300450.0 ; + RECT 33450.0 295350.0 34350.0 300000.0 ; + RECT 30900.0 302850.0 32100.0 304050.0 ; + RECT 33300.0 294150.0 34500.0 295350.0 ; + RECT 34500.0 299400.0 33300.0 300600.0 ; + RECT 31050.0 312450.0 31950.0 311550.0 ; + RECT 33450.0 312450.0 34350.0 311550.0 ; + RECT 31050.0 312000.0 31950.0 309150.0 ; + RECT 31500.0 312450.0 33900.0 311550.0 ; + RECT 33450.0 316650.0 34350.0 312000.0 ; + RECT 30900.0 309150.0 32100.0 307950.0 ; + RECT 33300.0 317850.0 34500.0 316650.0 ; + RECT 34500.0 312600.0 33300.0 311400.0 ; + RECT 31050.0 327150.0 31950.0 328050.0 ; + RECT 33450.0 327150.0 34350.0 328050.0 ; + RECT 31050.0 327600.0 31950.0 330450.0 ; + RECT 31500.0 327150.0 33900.0 328050.0 ; + RECT 33450.0 322950.0 34350.0 327600.0 ; + RECT 30900.0 330450.0 32100.0 331650.0 ; + RECT 33300.0 321750.0 34500.0 322950.0 ; + RECT 34500.0 327000.0 33300.0 328200.0 ; + RECT 31050.0 340050.0 31950.0 339150.0 ; + RECT 33450.0 340050.0 34350.0 339150.0 ; + RECT 31050.0 339600.0 31950.0 336750.0 ; + RECT 31500.0 340050.0 33900.0 339150.0 ; + RECT 33450.0 344250.0 34350.0 339600.0 ; + RECT 30900.0 336750.0 32100.0 335550.0 ; + RECT 33300.0 345450.0 34500.0 344250.0 ; + RECT 34500.0 340200.0 33300.0 339000.0 ; + RECT 31050.0 354750.0 31950.0 355650.0 ; + RECT 33450.0 354750.0 34350.0 355650.0 ; + RECT 31050.0 355200.0 31950.0 358050.0 ; + RECT 31500.0 354750.0 33900.0 355650.0 ; + RECT 33450.0 350550.0 34350.0 355200.0 ; + RECT 30900.0 358050.0 32100.0 359250.0 ; + RECT 33300.0 349350.0 34500.0 350550.0 ; + RECT 34500.0 354600.0 33300.0 355800.0 ; + RECT 31050.0 367650.0 31950.0 366750.0 ; + RECT 33450.0 367650.0 34350.0 366750.0 ; + RECT 31050.0 367200.0 31950.0 364350.0 ; + RECT 31500.0 367650.0 33900.0 366750.0 ; + RECT 33450.0 371850.0 34350.0 367200.0 ; + RECT 30900.0 364350.0 32100.0 363150.0 ; + RECT 33300.0 373050.0 34500.0 371850.0 ; + RECT 34500.0 367800.0 33300.0 366600.0 ; + RECT 31050.0 382350.0 31950.0 383250.0 ; + RECT 33450.0 382350.0 34350.0 383250.0 ; + RECT 31050.0 382800.0 31950.0 385650.0 ; + RECT 31500.0 382350.0 33900.0 383250.0 ; + RECT 33450.0 378150.0 34350.0 382800.0 ; + RECT 30900.0 385650.0 32100.0 386850.0 ; + RECT 33300.0 376950.0 34500.0 378150.0 ; + RECT 34500.0 382200.0 33300.0 383400.0 ; + RECT 31050.0 395250.0 31950.0 394350.0 ; + RECT 33450.0 395250.0 34350.0 394350.0 ; + RECT 31050.0 394800.0 31950.0 391950.0 ; + RECT 31500.0 395250.0 33900.0 394350.0 ; + RECT 33450.0 399450.0 34350.0 394800.0 ; + RECT 30900.0 391950.0 32100.0 390750.0 ; + RECT 33300.0 400650.0 34500.0 399450.0 ; + RECT 34500.0 395400.0 33300.0 394200.0 ; + RECT 31050.0 409950.0 31950.0 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RECT 10950.0 216600.0 9750.0 217800.0 ; + RECT 19350.0 213900.0 18150.0 215100.0 ; + RECT 10950.0 228600.0 9750.0 229800.0 ; + RECT 21450.0 231300.0 20250.0 232500.0 ; + RECT 10950.0 244200.0 9750.0 245400.0 ; + RECT 23550.0 241500.0 22350.0 242700.0 ; + RECT 10950.0 256200.0 9750.0 257400.0 ; + RECT 25650.0 258900.0 24450.0 260100.0 ; + RECT 13050.0 271800.0 11850.0 273000.0 ; + RECT 19350.0 269100.0 18150.0 270300.0 ; + RECT 13050.0 283800.0 11850.0 285000.0 ; + RECT 21450.0 286500.0 20250.0 287700.0 ; + RECT 13050.0 299400.0 11850.0 300600.0 ; + RECT 23550.0 296700.0 22350.0 297900.0 ; + RECT 13050.0 311400.0 11850.0 312600.0 ; + RECT 25650.0 314100.0 24450.0 315300.0 ; + RECT 15150.0 327000.0 13950.0 328200.0 ; + RECT 19350.0 324300.0 18150.0 325500.0 ; + RECT 15150.0 339000.0 13950.0 340200.0 ; + RECT 21450.0 341700.0 20250.0 342900.0 ; + RECT 15150.0 354600.0 13950.0 355800.0 ; + RECT 23550.0 351900.0 22350.0 353100.0 ; + RECT 15150.0 366600.0 13950.0 367800.0 ; + RECT 25650.0 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370350.0 ; + RECT 55350.0 369900.0 56250.0 370800.0 ; + RECT 55800.0 369450.0 72000.0 370350.0 ; + RECT 55350.0 379650.0 56250.0 380550.0 ; + RECT 55350.0 379200.0 56250.0 380100.0 ; + RECT 55800.0 379650.0 72000.0 380550.0 ; + RECT 55350.0 397050.0 56250.0 397950.0 ; + RECT 55350.0 397500.0 56250.0 398400.0 ; + RECT 55800.0 397050.0 72000.0 397950.0 ; + RECT 55350.0 407250.0 56250.0 408150.0 ; + RECT 55350.0 406800.0 56250.0 407700.0 ; + RECT 55800.0 407250.0 72000.0 408150.0 ; + RECT 55350.0 424650.0 56250.0 425550.0 ; + RECT 55350.0 425100.0 56250.0 426000.0 ; + RECT 55800.0 424650.0 72000.0 425550.0 ; + RECT 70950.0 216750.0 71850.0 217650.0 ; + RECT 73350.0 216750.0 74250.0 217650.0 ; + RECT 70950.0 217200.0 71850.0 220050.0 ; + RECT 71400.0 216750.0 73800.0 217650.0 ; + RECT 73350.0 212550.0 74250.0 217200.0 ; + RECT 70800.0 220050.0 72000.0 221250.0 ; + RECT 73200.0 211350.0 74400.0 212550.0 ; + RECT 74400.0 216600.0 73200.0 217800.0 ; + RECT 53250.0 215400.0 54450.0 216600.0 ; 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72000.0 241500.0 70800.0 242700.0 ; + RECT 70950.0 257250.0 71850.0 256350.0 ; + RECT 73350.0 257250.0 74250.0 256350.0 ; + RECT 70950.0 256800.0 71850.0 253950.0 ; + RECT 71400.0 257250.0 73800.0 256350.0 ; + RECT 73350.0 261450.0 74250.0 256800.0 ; + RECT 70800.0 253950.0 72000.0 252750.0 ; + RECT 73200.0 262650.0 74400.0 261450.0 ; + RECT 74400.0 257400.0 73200.0 256200.0 ; + RECT 53250.0 257400.0 54450.0 258600.0 ; + RECT 55200.0 259800.0 56400.0 261000.0 ; + RECT 72000.0 258900.0 70800.0 260100.0 ; + RECT 70950.0 271950.0 71850.0 272850.0 ; + RECT 73350.0 271950.0 74250.0 272850.0 ; + RECT 70950.0 272400.0 71850.0 275250.0 ; + RECT 71400.0 271950.0 73800.0 272850.0 ; + RECT 73350.0 267750.0 74250.0 272400.0 ; + RECT 70800.0 275250.0 72000.0 276450.0 ; + RECT 73200.0 266550.0 74400.0 267750.0 ; + RECT 74400.0 271800.0 73200.0 273000.0 ; + RECT 53250.0 270600.0 54450.0 271800.0 ; + RECT 55200.0 268200.0 56400.0 269400.0 ; + RECT 72000.0 269100.0 70800.0 270300.0 ; + RECT 70950.0 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; + RECT -10200.0 401700.0 -9000.0 402900.0 ; + RECT -10200.0 411300.0 -9000.0 412500.0 ; + RECT -10200.0 420900.0 -9000.0 422100.0 ; + RECT -10200.0 430500.0 -9000.0 431700.0 ; + RECT -10200.0 440100.0 -9000.0 441300.0 ; + RECT -10200.0 449700.0 -9000.0 450900.0 ; + RECT -24600.0 443700.0 -23400.0 444900.0 ; + RECT -24600.0 434100.0 -23400.0 435300.0 ; + RECT -24600.0 424500.0 -23400.0 425700.0 ; + RECT -24600.0 414900.0 -23400.0 416100.0 ; + RECT -24600.0 405300.0 -23400.0 406500.0 ; + RECT -24600.0 395700.0 -23400.0 396900.0 ; + RECT -10200.0 394500.0 -9000.0 395700.0 ; + RECT -10200.0 423300.0 -9000.0 424500.0 ; + RECT -10200.0 452100.0 -9000.0 453300.0 ; + RECT -24600.0 422100.0 -23400.0 423300.0 ; + RECT -36000.0 374700.0 -46200.0 360900.0 ; + RECT -36000.0 374700.0 -46200.0 388500.0 ; + RECT -36000.0 402300.0 -46200.0 388500.0 ; + RECT -36000.0 402300.0 -46200.0 416100.0 ; + RECT -36000.0 429900.0 -46200.0 416100.0 ; + RECT -39000.0 375300.0 -40200.0 433500.0 ; + RECT -42000.0 374100.0 -43200.0 432300.0 ; + RECT -35400.0 374100.0 -36600.0 432300.0 ; + RECT -45600.0 374100.0 -46800.0 432300.0 ; + RECT -30450.0 376200.0 -31650.0 377400.0 ; + RECT -30450.0 399600.0 -31650.0 400800.0 ; + RECT -30450.0 403800.0 -31650.0 405000.0 ; + RECT -30450.0 427200.0 -31650.0 428400.0 ; + RECT -30600.0 389700.0 -31800.0 390900.0 ; + RECT -30000.0 350100.0 -31200.0 351300.0 ; + RECT -36600.0 350700.0 -35400.0 351900.0 ; + RECT -46800.0 350700.0 -45600.0 351900.0 ; + RECT -33450.0 363000.0 -32250.0 364200.0 ; + RECT -33450.0 354900.0 -32250.0 356100.0 ; + RECT -40200.0 354900.0 -39000.0 356100.0 ; + RECT -8850.0 265050.0 -10050.0 263850.0 ; + RECT -8850.0 224100.0 -10050.0 222900.0 ; + RECT -16200.0 224100.0 -17400.0 222900.0 ; + RECT -16200.0 283950.0 -17400.0 282750.0 ; + RECT -18900.0 185250.0 -20100.0 184050.0 ; + RECT -22950.0 265050.0 -24150.0 263850.0 ; + RECT -25650.0 270450.0 -26850.0 269250.0 ; + RECT -22200.0 307800.0 -23400.0 306600.0 ; + RECT -22200.0 307800.0 -23400.0 306600.0 ; + RECT -22200.0 283950.0 -23400.0 282750.0 ; + RECT -24900.0 310800.0 -26100.0 309600.0 ; + RECT -24900.0 310800.0 -26100.0 309600.0 ; + RECT -24900.0 281250.0 -26100.0 280050.0 ; + RECT -10950.0 283950.0 -12150.0 282750.0 ; + RECT -9000.0 281250.0 -10200.0 280050.0 ; + RECT -7050.0 273150.0 -8250.0 271950.0 ; + RECT -38550.0 283950.0 -39750.0 282750.0 ; + RECT -36600.0 273150.0 -37800.0 271950.0 ; + RECT -34650.0 275850.0 -35850.0 274650.0 ; + RECT -22950.0 302100.0 -24150.0 303300.0 ; + RECT -22200.0 319200.0 -23400.0 320400.0 ; + RECT -36600.0 341700.0 -37800.0 342900.0 ; + RECT -23400.0 321900.0 -24600.0 323100.0 ; + RECT -2400.0 267750.0 -3600.0 266550.0 ; + RECT -16200.0 278550.0 -17400.0 277350.0 ; + RECT -30000.0 267750.0 -31200.0 266550.0 ; + RECT -43800.0 278550.0 -45000.0 277350.0 ; + RECT -3000.0 322050.0 -24000.0 322950.0 ; + RECT -3000.0 341850.0 -37200.0 342750.0 ; + RECT -3000.0 302250.0 -23550.0 303150.0 ; + RECT -3000.0 319350.0 -22800.0 320250.0 ; + RECT -3000.0 282900.0 -52800.0 283800.0 ; + RECT -3000.0 264000.0 -52800.0 264900.0 ; + RECT -3000.0 277500.0 -52800.0 278400.0 ; + RECT -3000.0 266700.0 -52800.0 267600.0 ; + RECT 110700.0 321900.0 109500.0 323100.0 ; + RECT -3300.0 322050.0 -4500.0 323250.0 ; + RECT 108000.0 341700.0 106800.0 342900.0 ; + RECT -3300.0 341850.0 -4500.0 343050.0 ; + RECT 102600.0 302100.0 101400.0 303300.0 ; + RECT -3300.0 302250.0 -4500.0 303450.0 ; + RECT 99900.0 319200.0 98700.0 320400.0 ; + RECT -3300.0 319350.0 -4500.0 320550.0 ; + RECT 105300.0 282750.0 104100.0 283950.0 ; + RECT -3300.0 282900.0 -4500.0 284100.0 ; + RECT 97200.0 263850.0 96000.0 265050.0 ; + RECT -3300.0 264000.0 -4500.0 265200.0 ; + RECT 7350.0 277350.0 6150.0 278550.0 ; + RECT -3300.0 277500.0 -4500.0 278700.0 ; + LAYER metal3 ; + RECT -3000.0 321750.0 110100.0 323250.0 ; + RECT -3000.0 341550.0 107400.0 343050.0 ; + RECT -3000.0 301950.0 102000.0 303450.0 ; + RECT -3000.0 319050.0 99300.0 320550.0 ; + RECT -3000.0 282600.0 104700.0 284100.0 ; + RECT -3000.0 263700.0 96600.0 265200.0 ; + RECT -3000.0 277200.0 6750.0 278700.0 ; + RECT 117150.0 16200.0 118650.0 161400.0 ; + RECT 127350.0 16200.0 128850.0 161400.0 ; + RECT 120900.0 0.0 122400.0 39900.0 ; + RECT 131100.0 0.0 132600.0 39900.0 ; + RECT 117000.0 161400.0 118800.0 163200.0 ; + RECT 127200.0 161400.0 129000.0 163200.0 ; + RECT 120600.0 40800.0 122400.0 42600.0 ; + RECT 130800.0 40800.0 132600.0 42600.0 ; + RECT 10800.0 89400.0 12600.0 87600.0 ; + RECT 10800.0 79200.0 12600.0 77400.0 ; + RECT 10800.0 69000.0 12600.0 67200.0 ; + RECT 10800.0 58800.0 12600.0 57000.0 ; + RECT 117150.0 15450.0 118950.0 17250.0 ; + RECT 127350.0 15450.0 129150.0 17250.0 ; + RECT 120900.0 0.0 122700.0 1800.0 ; + RECT 131100.0 0.0 132900.0 1800.0 ; + RECT 0.0 87600.0 10800.0 89100.0 ; + RECT 0.0 77400.0 10800.0 78900.0 ; + RECT 0.0 67200.0 10800.0 68700.0 ; + RECT 0.0 57000.0 10800.0 58500.0 ; + RECT -49650.0 241800.0 -51150.0 280650.0 ; + RECT -46200.0 240600.0 -47700.0 269850.0 ; + RECT -34050.0 241800.0 -35550.0 272550.0 ; + RECT -29250.0 241800.0 -30750.0 275250.0 ; + RECT -41850.0 241800.0 -43350.0 267150.0 ; + RECT -21450.0 241800.0 -22950.0 267150.0 ; + RECT -16050.0 223500.0 -17550.0 283350.0 ; + RECT -22050.0 283350.0 -23550.0 307200.0 ; + RECT -24750.0 280650.0 -26250.0 310200.0 ; + RECT -48600.0 182700.0 -46800.0 184500.0 ; + RECT -38400.0 182700.0 -36600.0 184500.0 ; + RECT -28200.0 182700.0 -26400.0 184500.0 ; + RECT -49500.0 242700.0 -51300.0 240900.0 ; + RECT -49500.0 281550.0 -51300.0 279750.0 ; + RECT -46050.0 241500.0 -47850.0 239700.0 ; + RECT -46050.0 270750.0 -47850.0 268950.0 ; + RECT -33900.0 242700.0 -35700.0 240900.0 ; + RECT -33900.0 273450.0 -35700.0 271650.0 ; + RECT -29100.0 242700.0 -30900.0 240900.0 ; + RECT -29100.0 276150.0 -30900.0 274350.0 ; + RECT -41700.0 242700.0 -43500.0 240900.0 ; + RECT -41700.0 268050.0 -43500.0 266250.0 ; + RECT -21300.0 242700.0 -23100.0 240900.0 ; + RECT -21300.0 268050.0 -23100.0 266250.0 ; + RECT -15900.0 224400.0 -17700.0 222600.0 ; + RECT -15900.0 284250.0 -17700.0 282450.0 ; + RECT -21900.0 308100.0 -23700.0 306300.0 ; + RECT -21900.0 284250.0 -23700.0 282450.0 ; + RECT -24600.0 311100.0 -26400.0 309300.0 ; + RECT -24600.0 281550.0 -26400.0 279750.0 ; + RECT -36600.0 182700.0 -38400.0 184500.0 ; + RECT -26400.0 182700.0 -28200.0 184500.0 ; + RECT -46800.0 182700.0 -48600.0 184500.0 ; + RECT 111000.0 321600.0 109200.0 323400.0 ; + RECT -3000.0 321750.0 -4800.0 323550.0 ; + RECT 108300.0 341400.0 106500.0 343200.0 ; + RECT -3000.0 341550.0 -4800.0 343350.0 ; + RECT 102900.0 301800.0 101100.0 303600.0 ; + RECT -3000.0 301950.0 -4800.0 303750.0 ; + RECT 100200.0 318900.0 98400.0 320700.0 ; + RECT -3000.0 319050.0 -4800.0 320850.0 ; + RECT 105600.0 282450.0 103800.0 284250.0 ; + RECT -3000.0 282600.0 -4800.0 284400.0 ; + RECT 97500.0 263550.0 95700.0 265350.0 ; + RECT -3000.0 263700.0 -4800.0 265500.0 ; + RECT 7650.0 277050.0 5850.0 278850.0 ; + RECT -3000.0 277200.0 -4800.0 279000.0 ; + END + END sram_2_16_1_scn3me_subm +END LIBRARY diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.sp b/compiler/tests/golden/sram_2_16_1_scn4m_subm.sp new file mode 100644 index 00000000..258b4464 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.sp @@ -0,0 +1,681 @@ +* OpenRAM generated memory. +* User: mrg +.global vdd gnd +*master-slave flip-flop with both output and inverted ouput + +.subckt ms_flop din dout dout_bar clk vdd gnd +xmaster din mout mout_bar clk clk_bar vdd gnd dlatch +xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch +.ends flop + +.subckt dlatch din dout dout_bar clk clk_bar vdd gnd +*clk inverter +mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1 +mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1 + +*transmission gate 1 +mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1 +mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1 + +*foward inverter +mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1 +mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1 + +*backward inverter +mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1 +mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1 + +*transmission gate 2 +mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1 +mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1 +.ends dlatch + + +.SUBCKT inv_nmos11 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos11 + +.SUBCKT inv_pmos12 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS inv_pmos12 + +.SUBCKT pinv A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos11 +Xpinv_pmos Z A vdd vdd inv_pmos12 +.ENDS pinv + +.SUBCKT nand_2_nmos13 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos13 + +.SUBCKT nand_2_nmos24 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos24 + +.SUBCKT nand_2_pmos15 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos15 + +.SUBCKT nand_2_pmos26 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos26 + +.SUBCKT nand2 A B Z vdd gnd +Xnmos1 Z A net1 gnd nand_2_nmos13 +Xnmos2 net1 B gnd gnd nand_2_nmos24 +Xpmos1 vdd A Z vdd nand_2_pmos15 +Xpmos2 Z B vdd vdd nand_2_pmos26 +.ENDS nand2 + +.SUBCKT nand_3_nmos17 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos17 + +.SUBCKT nand_3_nmos28 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos28 + +.SUBCKT nand_3_nmos39 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos39 + +.SUBCKT nand_3_pmos110 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos110 + +.SUBCKT nand_3_pmos211 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos211 + +.SUBCKT nand_3_pmos312 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos312 + +.SUBCKT NAND3 A B C Z vdd gnd +Xnmos1 net2 A gnd gnd nand_3_nmos17 +Xnmos2 net1 B net2 gnd nand_3_nmos28 +Xnmos3 Z C net1 gnd nand_3_nmos39 +Xpmos1 Z A vdd vdd nand_3_pmos110 +Xpmos2 vdd B Z vdd nand_3_pmos211 +Xpmos3 Z C vdd vdd nand_3_pmos312 +.ENDS NAND3 + +.SUBCKT inv_nmos113 D G S B +Mnmos D G S B n m=4 w=1.2u l=0.6u +.ENDS inv_nmos113 + +.SUBCKT inv_pmos114 D G S B +Mpmos D G S B p m=4 w=2.4u l=0.6u +.ENDS inv_pmos114 + +.SUBCKT pinv4 A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos113 +Xpinv_pmos Z A vdd vdd inv_pmos114 +.ENDS pinv4 + +.SUBCKT nor_2_nmos123 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos123 + +.SUBCKT nor_2_nmos224 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos224 + +.SUBCKT nor_2_pmos125 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos125 + +.SUBCKT nor_2_pmos226 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos226 + +.SUBCKT nor2 A B Z vdd gnd +Xnmos1 Z A gnd gnd nor_2_nmos123 +Xnmos2 Z B gnd gnd nor_2_nmos224 +Xpmos1 vdd A net1 vdd nor_2_pmos125 +Xpmos2 net1 B Z vdd nor_2_pmos226 +.ENDS nor2 + +.SUBCKT msf_control DATA[0] DATA[1] DATA[2] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] data_in[2] data_in_bar[2] clk vdd gnd +XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop +XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop +XXdff2 DATA[2] data_in[2] data_in_bar[2] clk vdd gnd ms_flop +.ENDS msf_control + +*********************** "cell_6t" ****************************** +.SUBCKT replica_cell_6t bl br wl vdd gnd +M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u +M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u +M_3 br wl net_2 gnd n W='1.2u' L=0.6u +M_4 bl wl gnd gnd n W='1.2u' L=0.6u +M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u +M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u +.ENDS $ replica_cell_6t + +*********************** "cell_6t" ****************************** +.SUBCKT cell_6t bl br wl vdd gnd +M_1 net_1 net_2 vdd vdd p W='0.9u' L=1.2u +M_2 net_2 net_1 vdd vdd p W='0.9u' L=1.2u +M_3 br wl net_2 gnd n W='1.2u' L=0.6u +M_4 bl wl net_1 gnd n W='1.2u' L=0.6u +M_5 net_2 net_1 gnd gnd n W='2.4u' L=0.6u +M_6 net_1 net_2 gnd gnd n W='2.4u' L=0.6u +.ENDS $ cell_6t + +.SUBCKT bitline_load bl[0] br[0] wl[0] wl[1] vdd gnd +Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t +Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t +.ENDS bitline_load + +.SUBCKT inv_nmos127 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos127 + +.SUBCKT inv_pmos128 D G S B +Mpmos D G S B p m=1 w=3.6u l=0.6u +.ENDS inv_pmos128 + +.SUBCKT delay_chain_inv A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos127 +Xpinv_pmos Z A vdd vdd inv_pmos128 +.ENDS delay_chain_inv + +.SUBCKT delay_chain clk_in clk_out vdd gnd +Xinv_chain0 clk_in s1 vdd gnd delay_chain_inv +Xinv_chain1 s1 s2 vdd gnd delay_chain_inv +Xinv_chain2 s2 s3 vdd gnd delay_chain_inv +Xinv_chain3 s3 clk_out vdd gnd delay_chain_inv +.ENDS delay_chain + +.SUBCKT inv_nmos129 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos129 + +.SUBCKT inv_pmos130 D G S B +Mpmos D G S B p m=1 w=3.6u l=0.6u +.ENDS inv_pmos130 + +.SUBCKT RBL_inv A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos129 +Xpinv_pmos Z A vdd vdd inv_pmos130 +.ENDS RBL_inv + +.SUBCKT nor_2_nmos139 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos139 + +.SUBCKT nor_2_nmos240 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos240 + +.SUBCKT nor_2_pmos141 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos141 + +.SUBCKT nor_2_pmos242 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos242 + +.SUBCKT replica_bitline_nor2 A B Z vdd gnd +Xnmos1 Z A gnd gnd nor_2_nmos139 +Xnmos2 Z B gnd gnd nor_2_nmos240 +Xpmos1 vdd A net1 vdd nor_2_pmos141 +Xpmos2 net1 B Z vdd nor_2_pmos242 +.ENDS replica_bitline_nor2 + +.SUBCKT access_tx43 D G S B +Mpmos D G S B p m=1 w=1.2u l=0.6u +.ENDS access_tx43 + +.SUBCKT replica_bitline en out vdd gnd +XBL_inv bl[0] out vdd gnd RBL_inv +XBL_access_tx vdd delayed_en bl[0] vdd access_tx43 +Xdelay_chain en delayed_en vdd gnd delay_chain +Xbitcell bl[0] br[0] delayed_en vdd gnd replica_cell_6t +Xload bl[0] br[0] gnd gnd vdd gnd bitline_load +.ENDS replica_bitline + +.SUBCKT control_logic CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd +Xmsf_control CSb WEb OEb CS_bar CS WE_bar WE OE_bar OE clk vdd gnd msf_control +Xclk_inverter clk clk_bar vdd gnd pinv4 +Xnor2 clk OE_bar tri_en vdd gnd nor2 +Xnand2_tri_en OE clk_bar tri_en_bar vdd gnd nand2 +Xreplica_bitline rblk pre_s_en vdd gnd replica_bitline +Xinv_s_en1 pre_s_en_bar s_en vdd gnd pinv +Xinv_s_en2 pre_s_en pre_s_en_bar vdd gnd pinv +XNAND3_rblk_bar clk_bar OE CS rblk_bar vdd gnd NAND3 +XNAND3_w_en_bar clk_bar WE CS w_en_bar vdd gnd NAND3 +Xinv_rblk rblk_bar rblk vdd gnd pinv +Xinv_w_en w_en_bar pre_w_en vdd gnd pinv +Xinv_w_en1 pre_w_en pre_w_en1 vdd gnd pinv +Xinv_w_en2 pre_w_en1 w_en vdd gnd pinv +.ENDS control_logic + +.SUBCKT bitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd +Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t +Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t +Xbit_r2_c0 bl[0] br[0] wl[2] vdd gnd cell_6t +Xbit_r3_c0 bl[0] br[0] wl[3] vdd gnd cell_6t +Xbit_r4_c0 bl[0] br[0] wl[4] vdd gnd cell_6t +Xbit_r5_c0 bl[0] br[0] wl[5] vdd gnd cell_6t +Xbit_r6_c0 bl[0] br[0] wl[6] vdd gnd cell_6t +Xbit_r7_c0 bl[0] br[0] wl[7] vdd gnd cell_6t +Xbit_r8_c0 bl[0] br[0] wl[8] vdd gnd cell_6t +Xbit_r9_c0 bl[0] br[0] wl[9] vdd gnd cell_6t +Xbit_r10_c0 bl[0] br[0] wl[10] vdd gnd cell_6t +Xbit_r11_c0 bl[0] br[0] wl[11] vdd gnd cell_6t +Xbit_r12_c0 bl[0] br[0] wl[12] vdd gnd cell_6t +Xbit_r13_c0 bl[0] br[0] wl[13] vdd gnd cell_6t +Xbit_r14_c0 bl[0] br[0] wl[14] vdd gnd cell_6t +Xbit_r15_c0 bl[0] br[0] wl[15] vdd gnd cell_6t +Xbit_r0_c1 bl[1] br[1] wl[0] vdd gnd cell_6t +Xbit_r1_c1 bl[1] br[1] wl[1] vdd gnd cell_6t +Xbit_r2_c1 bl[1] br[1] wl[2] vdd gnd cell_6t +Xbit_r3_c1 bl[1] br[1] wl[3] vdd gnd cell_6t +Xbit_r4_c1 bl[1] br[1] wl[4] vdd gnd cell_6t +Xbit_r5_c1 bl[1] br[1] wl[5] vdd gnd cell_6t +Xbit_r6_c1 bl[1] br[1] wl[6] vdd gnd cell_6t +Xbit_r7_c1 bl[1] br[1] wl[7] vdd gnd cell_6t +Xbit_r8_c1 bl[1] br[1] wl[8] vdd gnd cell_6t +Xbit_r9_c1 bl[1] br[1] wl[9] vdd gnd cell_6t +Xbit_r10_c1 bl[1] br[1] wl[10] vdd gnd cell_6t +Xbit_r11_c1 bl[1] br[1] wl[11] vdd gnd cell_6t +Xbit_r12_c1 bl[1] br[1] wl[12] vdd gnd cell_6t +Xbit_r13_c1 bl[1] br[1] wl[13] vdd gnd cell_6t +Xbit_r14_c1 bl[1] br[1] wl[14] vdd gnd cell_6t +Xbit_r15_c1 bl[1] br[1] wl[15] vdd gnd cell_6t +.ENDS bitcell_array + +.SUBCKT lower_pmos44 D G S B +Mpmos D G S B p m=1 w=1.2u l=0.6u +.ENDS lower_pmos44 + +.SUBCKT upper_pmos45 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS upper_pmos45 + +.SUBCKT precharge_cell bl br clk vdd +Xlower_pmos bl clk br vdd lower_pmos44 +Xupper_pmos1 bl clk vdd vdd upper_pmos45 +Xupper_pmos2 br clk vdd vdd upper_pmos45 +.ENDS precharge_cell + +.SUBCKT precharge_array bl[0] br[0] bl[1] br[1] clk vdd +Xpre_column_0 bl[0] br[0] clk vdd precharge_cell +Xpre_column_1 bl[1] br[1] clk vdd precharge_cell +.ENDS precharge_array +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout sclk vdd gnd +M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u +M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u +M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u +M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u +M_5 bl sclk dout vdd p W='7.2*1u' L=0.6u +M_6 br sclk net_1 vdd p W='7.2*1u' L=0.6u +M_7 net_2 sclk gnd gnd n W='2.7*1u' L=0.6u +.ENDS sense_amp + + +.SUBCKT sense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] sclk vdd gnd +Xsa_d0 bl[0] br[0] data_out[0] sclk vdd gnd sense_amp +Xsa_d1 bl[1] br[1] data_out[1] sclk vdd gnd sense_amp +.ENDS sense_amp_array +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br wen vdd gnd + +**** Inverter to conver Data_in to data_in_bar ****** +M_1 net_3 din gnd gnd n W='1.2*1u' L=0.6u +M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u + +**** 2input nand gate follwed by inverter to drive BL ****** +M_3 net_2 wen net_7 gnd n W='2.1*1u' L=0.6u +M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u +M_5 net_2 wen vdd vdd p W='2.1*1u' L=0.6u +M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u + + +M_7 net_1 net_2 vdd vdd p W='2.1*1u' L=0.6u +M_8 net_1 net_2 gnd gnd n W='1.2*1u' L=0.6u + +**** 2input nand gate follwed by inverter to drive BR****** + +M_9 net_4 wen vdd vdd p W='2.1*1u' L=0.6u +M_10 net_4 wen net_8 gnd n W='2.1*1u' L=0.6u +M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u +M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u + +M_13 net_6 net_4 vdd vdd p W='2.1*1u' L=0.6u +M_14 net_6 net_4 gnd gnd n W='1.2*1u' L=0.6u + +************************************************ + +M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u +M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u +M_17 net_5 wen gnd gnd n W='3.6*1u' L=0.6u + + + +.ENDS $ write_driver + + +.SUBCKT write_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] wen vdd gnd +XXwrite_driver0 data_in[0] bl[0] br[0] wen vdd gnd write_driver +XXwrite_driver1 data_in[1] bl[1] br[1] wen vdd gnd write_driver +.ENDS write_driver_array + +.SUBCKT inv_nmos147 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos147 + +.SUBCKT inv_pmos148 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS inv_pmos148 + +.SUBCKT INVERTER A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos147 +Xpinv_pmos Z A vdd vdd inv_pmos148 +.ENDS INVERTER + +.SUBCKT nand_2_nmos149 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos149 + +.SUBCKT nand_2_nmos250 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos250 + +.SUBCKT nand_2_pmos151 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos151 + +.SUBCKT nand_2_pmos252 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos252 + +.SUBCKT NAND2 A B Z vdd gnd +Xnmos1 Z A net1 gnd nand_2_nmos149 +Xnmos2 net1 B gnd gnd nand_2_nmos250 +Xpmos1 vdd A Z vdd nand_2_pmos151 +Xpmos2 Z B vdd vdd nand_2_pmos252 +.ENDS NAND2 + +.SUBCKT nand_2_nmos159 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos159 + +.SUBCKT nand_2_nmos260 D G S B +Mnmos D G S B n m=1 w=2.4u l=0.6u +.ENDS nand_2_nmos260 + +.SUBCKT nand_2_pmos161 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos161 + +.SUBCKT nand_2_pmos262 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_2_pmos262 + +.SUBCKT a_nand_2 A B Z vdd gnd +Xnmos1 Z A net1 gnd nand_2_nmos159 +Xnmos2 net1 B gnd gnd nand_2_nmos260 +Xpmos1 vdd A Z vdd nand_2_pmos161 +Xpmos2 Z B vdd vdd nand_2_pmos262 +.ENDS a_nand_2 + +.SUBCKT inv_nmos163 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS inv_nmos163 + +.SUBCKT inv_pmos164 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS inv_pmos164 + +.SUBCKT a_inv_1 A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos163 +Xpinv_pmos Z A vdd vdd inv_pmos164 +.ENDS a_inv_1 + +.SUBCKT pre2x4 A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd +XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1 +XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1 +XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1 +XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1 +XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1 +XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1 +XXpre2x4_nand[0] A[0] A[1] Z[3] vdd gnd a_nand_2 +XXpre2x4_nand[1] B[0] A[1] Z[2] vdd gnd a_nand_2 +XXpre2x4_nand[2] A[0] B[1] Z[1] vdd gnd a_nand_2 +XXpre2x4_nand[3] B[0] B[1] Z[0] vdd gnd a_nand_2 +.ENDS pre2x4 + +.SUBCKT nand_3_nmos165 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos165 + +.SUBCKT nand_3_nmos266 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos266 + +.SUBCKT nand_3_nmos367 D G S B +Mnmos D G S B n m=1 w=3.6u l=0.6u +.ENDS nand_3_nmos367 + +.SUBCKT nand_3_pmos168 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos168 + +.SUBCKT nand_3_pmos269 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos269 + +.SUBCKT nand_3_pmos370 D G S B +Mpmos D G S B p m=1 w=2.4u l=0.6u +.ENDS nand_3_pmos370 + +.SUBCKT a_nand_3 A B C Z vdd gnd +Xnmos1 net2 A gnd gnd nand_3_nmos165 +Xnmos2 net1 B net2 gnd nand_3_nmos266 +Xnmos3 Z C net1 gnd nand_3_nmos367 +Xpmos1 Z A vdd vdd nand_3_pmos168 +Xpmos2 vdd B Z vdd nand_3_pmos269 +Xpmos3 Z C vdd vdd nand_3_pmos370 +.ENDS a_nand_3 + +.SUBCKT pre3x8 A[0] A[1] A[2] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] vdd gnd +XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1 +XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1 +XXpre2x4_inv[2] A[2] B[2] vdd gnd a_inv_1 +XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1 +XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1 +XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1 +XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1 +XXpre2x4_nand_inv[4] Z[4] out[4] vdd gnd a_inv_1 +XXpre2x4_nand_inv[5] Z[5] out[5] vdd gnd a_inv_1 +XXpre2x4_nand_inv[6] Z[6] out[6] vdd gnd a_inv_1 +XXpre2x4_nand_inv[7] Z[7] out[7] vdd gnd a_inv_1 +XXpre3x8_nand[0] A[0] A[1] A[2] Z[7] vdd gnd a_nand_3 +XXpre3x8_nand[1] A[0] A[1] B[2] Z[6] vdd gnd a_nand_3 +XXpre3x8_nand[2] A[0] B[1] A[2] Z[5] vdd gnd a_nand_3 +XXpre3x8_nand[3] A[0] B[1] B[2] Z[4] vdd gnd a_nand_3 +XXpre3x8_nand[4] B[0] A[1] A[2] Z[3] vdd gnd a_nand_3 +XXpre3x8_nand[5] B[0] A[1] B[2] Z[2] vdd gnd a_nand_3 +XXpre3x8_nand[6] B[0] B[1] A[2] Z[1] vdd gnd a_nand_3 +XXpre3x8_nand[7] B[0] B[1] B[2] Z[0] vdd gnd a_nand_3 +.ENDS pre3x8 + +.SUBCKT hierarchical_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd +Xpre[0] A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd pre2x4 +Xpre[1] A[2] A[3] out[4] out[5] out[6] out[7] vdd gnd pre2x4 +XNAND2_[0] out[0] out[4] Z[0] vdd gnd NAND2 +XNAND2_[1] out[0] out[5] Z[1] vdd gnd NAND2 +XNAND2_[2] out[0] out[6] Z[2] vdd gnd NAND2 +XNAND2_[3] out[0] out[7] Z[3] vdd gnd NAND2 +XNAND2_[4] out[1] out[4] Z[4] vdd gnd NAND2 +XNAND2_[5] out[1] out[5] Z[5] vdd gnd NAND2 +XNAND2_[6] out[1] out[6] Z[6] vdd gnd NAND2 +XNAND2_[7] out[1] out[7] Z[7] vdd gnd NAND2 +XNAND2_[8] out[2] out[4] Z[8] vdd gnd NAND2 +XNAND2_[9] out[2] out[5] Z[9] vdd gnd NAND2 +XNAND2_[10] out[2] out[6] Z[10] vdd gnd NAND2 +XNAND2_[11] out[2] out[7] Z[11] vdd gnd NAND2 +XNAND2_[12] out[3] out[4] Z[12] vdd gnd NAND2 +XNAND2_[13] out[3] out[5] Z[13] vdd gnd NAND2 +XNAND2_[14] out[3] out[6] Z[14] vdd gnd NAND2 +XNAND2_[15] out[3] out[7] Z[15] vdd gnd NAND2 +XINVERTER_[0] Z[0] decode_out[0] vdd gnd INVERTER +XINVERTER_[1] Z[1] decode_out[1] vdd gnd INVERTER +XINVERTER_[2] Z[2] decode_out[2] vdd gnd INVERTER +XINVERTER_[3] Z[3] decode_out[3] vdd gnd INVERTER +XINVERTER_[4] Z[4] decode_out[4] vdd gnd INVERTER +XINVERTER_[5] Z[5] decode_out[5] vdd gnd INVERTER +XINVERTER_[6] Z[6] decode_out[6] vdd gnd INVERTER +XINVERTER_[7] Z[7] decode_out[7] vdd gnd INVERTER +XINVERTER_[8] Z[8] decode_out[8] vdd gnd INVERTER +XINVERTER_[9] Z[9] decode_out[9] vdd gnd INVERTER +XINVERTER_[10] Z[10] decode_out[10] vdd gnd INVERTER +XINVERTER_[11] Z[11] decode_out[11] vdd gnd INVERTER +XINVERTER_[12] Z[12] decode_out[12] vdd gnd INVERTER +XINVERTER_[13] Z[13] decode_out[13] vdd gnd INVERTER +XINVERTER_[14] Z[14] decode_out[14] vdd gnd INVERTER +XINVERTER_[15] Z[15] decode_out[15] vdd gnd INVERTER +.ENDS hierarchical_decoder + +.SUBCKT msf_address ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] addr_clk vdd gnd +XXdff0 ADDR[0] A[0] A_bar[0] addr_clk vdd gnd ms_flop +XXdff1 ADDR[1] A[1] A_bar[1] addr_clk vdd gnd ms_flop +XXdff2 ADDR[2] A[2] A_bar[2] addr_clk vdd gnd ms_flop +XXdff3 ADDR[3] A[3] A_bar[3] addr_clk vdd gnd ms_flop +.ENDS msf_address + +.SUBCKT msf_data_in DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk vdd gnd +XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop +XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop +.ENDS msf_data_in + +.SUBCKT msf_data_out data_out[0] data_out[1] tri_in[0] tri_in_bar[0] tri_in[1] tri_in_bar[1] sclk vdd gnd +XXdff0 data_out[0] tri_in[0] tri_in_bar[0] sclk vdd gnd ms_flop +XXdff1 data_out[1] tri_in[1] tri_in_bar[1] sclk vdd gnd ms_flop +.ENDS msf_data_out +*********************** tri_gate ****************************** + +.SUBCKT tri_gate in out en en_bar vdd gnd + +M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u +M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u +M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u +M_4 out en net_2 gnd n W='1.2*1u' L=0.6u +M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u +M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u + + +.ENDS + +.SUBCKT tri_gate_array tri_in[0] tri_in[1] DATA[0] DATA[1] en en_bar vdd gnd +XXtri_gate0 tri_in[0] DATA[0] en en_bar vdd gnd tri_gate +XXtri_gate1 tri_in[1] DATA[1] en en_bar vdd gnd tri_gate +.ENDS tri_gate_array + +.SUBCKT wordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd +XWordline_driver_inv_clk0 clk clk_bar[0] vdd gnd INVERTER +XWordline_driver_nand0 decode_out[0] clk_bar[0] net[0] vdd gnd NAND2 +XWordline_driver_inv0 net[0] wl[0] vdd gnd INVERTER +XWordline_driver_inv_clk1 clk clk_bar[1] vdd gnd INVERTER +XWordline_driver_nand1 decode_out[1] clk_bar[1] net[1] vdd gnd NAND2 +XWordline_driver_inv1 net[1] wl[1] vdd gnd INVERTER +XWordline_driver_inv_clk2 clk clk_bar[2] vdd gnd INVERTER +XWordline_driver_nand2 decode_out[2] clk_bar[2] net[2] vdd gnd NAND2 +XWordline_driver_inv2 net[2] wl[2] vdd gnd INVERTER +XWordline_driver_inv_clk3 clk clk_bar[3] vdd gnd INVERTER +XWordline_driver_nand3 decode_out[3] clk_bar[3] net[3] vdd gnd NAND2 +XWordline_driver_inv3 net[3] wl[3] vdd gnd INVERTER +XWordline_driver_inv_clk4 clk clk_bar[4] vdd gnd INVERTER +XWordline_driver_nand4 decode_out[4] clk_bar[4] net[4] vdd gnd NAND2 +XWordline_driver_inv4 net[4] wl[4] vdd gnd INVERTER +XWordline_driver_inv_clk5 clk clk_bar[5] vdd gnd INVERTER +XWordline_driver_nand5 decode_out[5] clk_bar[5] net[5] vdd gnd NAND2 +XWordline_driver_inv5 net[5] wl[5] vdd gnd INVERTER +XWordline_driver_inv_clk6 clk clk_bar[6] vdd gnd INVERTER +XWordline_driver_nand6 decode_out[6] clk_bar[6] net[6] vdd gnd NAND2 +XWordline_driver_inv6 net[6] wl[6] vdd gnd INVERTER +XWordline_driver_inv_clk7 clk clk_bar[7] vdd gnd INVERTER +XWordline_driver_nand7 decode_out[7] clk_bar[7] net[7] vdd gnd NAND2 +XWordline_driver_inv7 net[7] wl[7] vdd gnd INVERTER +XWordline_driver_inv_clk8 clk clk_bar[8] vdd gnd INVERTER +XWordline_driver_nand8 decode_out[8] clk_bar[8] net[8] vdd gnd NAND2 +XWordline_driver_inv8 net[8] wl[8] vdd gnd INVERTER +XWordline_driver_inv_clk9 clk clk_bar[9] vdd gnd INVERTER +XWordline_driver_nand9 decode_out[9] clk_bar[9] net[9] vdd gnd NAND2 +XWordline_driver_inv9 net[9] wl[9] vdd gnd INVERTER +XWordline_driver_inv_clk10 clk clk_bar[10] vdd gnd INVERTER +XWordline_driver_nand10 decode_out[10] clk_bar[10] net[10] vdd gnd NAND2 +XWordline_driver_inv10 net[10] wl[10] vdd gnd INVERTER +XWordline_driver_inv_clk11 clk clk_bar[11] vdd gnd INVERTER +XWordline_driver_nand11 decode_out[11] clk_bar[11] net[11] vdd gnd NAND2 +XWordline_driver_inv11 net[11] wl[11] vdd gnd INVERTER +XWordline_driver_inv_clk12 clk clk_bar[12] vdd gnd INVERTER +XWordline_driver_nand12 decode_out[12] clk_bar[12] net[12] vdd gnd NAND2 +XWordline_driver_inv12 net[12] wl[12] vdd gnd INVERTER +XWordline_driver_inv_clk13 clk clk_bar[13] vdd gnd INVERTER +XWordline_driver_nand13 decode_out[13] clk_bar[13] net[13] vdd gnd NAND2 +XWordline_driver_inv13 net[13] wl[13] vdd gnd INVERTER +XWordline_driver_inv_clk14 clk clk_bar[14] vdd gnd INVERTER +XWordline_driver_nand14 decode_out[14] clk_bar[14] net[14] vdd gnd NAND2 +XWordline_driver_inv14 net[14] wl[14] vdd gnd INVERTER +XWordline_driver_inv_clk15 clk clk_bar[15] vdd gnd INVERTER +XWordline_driver_nand15 decode_out[15] clk_bar[15] net[15] vdd gnd NAND2 +XWordline_driver_inv15 net[15] wl[15] vdd gnd INVERTER +.ENDS wordline_driver + +.SUBCKT inv_nmos181 D G S B +Mnmos D G S B n m=4 w=1.2u l=0.6u +.ENDS inv_nmos181 + +.SUBCKT inv_pmos182 D G S B +Mpmos D G S B p m=4 w=2.4u l=0.6u +.ENDS inv_pmos182 + +.SUBCKT pinv4x A Z vdd gnd +Xpinv_nmos Z A gnd gnd inv_nmos181 +Xpinv_pmos Z A vdd vdd inv_pmos182 +.ENDS pinv4x + +.SUBCKT nor_2_nmos195 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos195 + +.SUBCKT nor_2_nmos296 D G S B +Mnmos D G S B n m=1 w=1.2u l=0.6u +.ENDS nor_2_nmos296 + +.SUBCKT nor_2_pmos197 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos197 + +.SUBCKT nor_2_pmos298 D G S B +Mpmos D G S B p m=4 w=1.2u l=0.6u +.ENDS nor_2_pmos298 + +.SUBCKT NOR2 A B Z vdd gnd +Xnmos1 Z A gnd gnd nor_2_nmos195 +Xnmos2 Z B gnd gnd nor_2_nmos296 +Xpmos1 vdd A net1 vdd nor_2_pmos197 +Xpmos2 net1 B Z vdd nor_2_pmos298 +.ENDS NOR2 + +.SUBCKT test_bank1 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd +Xbitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd bitcell_array +Xprecharge_array bl[0] br[0] bl[1] br[1] clk_bar vdd precharge_array +Xsense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] s_en vdd gnd sense_amp_array +Xwrite_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] w_en vdd gnd write_driver_array +Xdata_in_flop_array DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk_bar vdd gnd msf_data_in +Xtrigate_data_array data_out[0] data_out[1] DATA[0] DATA[1] tri_en tri_en_bar vdd gnd tri_gate_array +Xaddress_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd hierarchical_decoder +Xwordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd wordline_driver +Xaddress_flop_array ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] clk vdd gnd msf_address +.ENDS test_bank1 + +.SUBCKT testsram DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] CSb WEb OEb clk vdd gnd +Xbank0 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd test_bank1 +Xcontrol CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd control_logic +.ENDS testsram diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v new file mode 100644 index 00000000..de4c077c --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v @@ -0,0 +1,47 @@ +// OpenRAM SRAM model +// Words: 16 +// Word size: 2 + +module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk); + + parameter DATA_WIDTH = 2 ; + parameter ADDR_WIDTH = 4 ; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + parameter DELAY = 3 ; + + inout [DATA_WIDTH-1:0] DATA; + input [ADDR_WIDTH-1:0] ADDR; + input CSb; // active low chip select + input WEb; // active low write control + input OEb; // active output enable + input clk; // clock + + reg [DATA_WIDTH-1:0] data_out ; + reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + + // Tri-State Buffer control + // output : When WEb = 1, oeb = 0, csb = 0 + assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz; + + // Memory Write Block + // Write Operation : When WEb = 0, CSb = 0 + always @ (posedge clk) + begin : MEM_WRITE + if ( !CSb && !WEb ) begin + mem[ADDR] = DATA; + $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA); + end + end + + + // Memory Read Block + // Read Operation : When WEb = 1, CSb = 0 + always @ (posedge clk) + begin : MEM_READ + if (!CSb && WEb) begin + data_out <= #(DELAY) mem[ADDR]; + $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]); + end + end + +endmodule diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib new file mode 100644 index 00000000..89f40320 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -0,0 +1,318 @@ +library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 60176.520000000004; + + leakage_power () { + when : "CSb0"; + value : 0.000175; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk; + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + cell_fall(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk & !WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "!CSb0 & !clk & WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + } +} diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib new file mode 100644 index 00000000..89f40320 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -0,0 +1,318 @@ +library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 60176.520000000004; + + leakage_power () { + when : "CSb0"; + value : 0.000175; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk; + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + cell_fall(CELL_TABLE) { + values("0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268",\ + "0.268, 0.268, 0.268"); + } + rise_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + fall_transition(CELL_TABLE) { + values("0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004",\ + "0.004, 0.004, 0.004"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009",\ + "0.009, 0.009, 0.009"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001",\ + "0.001, 0.001, 0.001"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk & !WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "!CSb0 & !clk & WEb0"; + rise_power(scalar){ + values("11.3007276371"); + } + fall_power(scalar){ + values("11.3007276371"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("0.0"); + } + fall_constraint(scalar) { + values("0.0"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("0"); + } + fall_constraint(scalar) { + values("0"); + } + } + } + } +} diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib new file mode 100644 index 00000000..8509fc30 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -0,0 +1,318 @@ +library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 5.0 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : OC; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn4m_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 60176.520000000004; + + leakage_power () { + when : "CSb0"; + value : 0.025716199999999998; + } + cell_leakage_power : 0; + bus(DIN0){ + bus_type : DATA; + direction : input; + capacitance : 9.8242; + memory_write(){ + address : ADDR0; + clocked_on : clk; + } + } + bus(DOUT0){ + bus_type : DATA; + direction : output; + max_capacitance : 78.5936; + min_capacitance : 2.45605; + memory_read(){ + address : ADDR0; + } + pin(DOUT0[1:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : rising_edge; + cell_rise(CELL_TABLE) { + values("1.277, 1.297, 1.475",\ + "1.28, 1.3, 1.479",\ + "1.347, 1.367, 1.545"); + } + cell_fall(CELL_TABLE) { + values("3.217, 3.281, 3.71",\ + "3.22, 3.285, 3.714",\ + "3.261, 3.325, 3.75"); + } + rise_transition(CELL_TABLE) { + values("0.122, 0.164, 0.579",\ + "0.122, 0.164, 0.578",\ + "0.122, 0.164, 0.58"); + } + fall_transition(CELL_TABLE) { + values("0.363, 0.396, 0.958",\ + "0.363, 0.396, 0.957",\ + "0.366, 0.399, 0.951"); + } + } + } + } + + bus(ADDR0){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + pin(ADDR0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + } + } + + pin(CSb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + } + + pin(WEb0){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228",\ + "0.179, 0.173, 0.228"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143",\ + "0.125, 0.125, 0.143"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114",\ + "-0.065, -0.071, -0.114"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095",\ + "-0.089, -0.089, -0.095"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 9.8242; + internal_power(){ + when : "!CSb0 & clk & !WEb0"; + rise_power(scalar){ + values("9.141838916666668"); + } + fall_power(scalar){ + values("9.141838916666668"); + } + } + internal_power(){ + when : "!CSb0 & !clk & WEb0"; + rise_power(scalar){ + values("8.304491694444444"); + } + fall_power(scalar){ + values("8.304491694444444"); + } + } + internal_power(){ + when : "CSb0"; + rise_power(scalar){ + values("0"); + } + fall_power(scalar){ + values("0"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("2.344"); + } + fall_constraint(scalar) { + values("2.344"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("4.688"); + } + fall_constraint(scalar) { + values("4.688"); + } + } + } + } +} diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index 64c1c2b4..79333318 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -183,6 +183,9 @@ class openram_test(unittest.TestCase): # 4. Check if remaining string matches if line1 != line2: + #Uncomment if you want to see all the individual chars of the two lines + #print(str([i for i in line1])) + #print(str([i for i in line2])) if mismatches==0: debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) mismatches += 1 @@ -222,17 +225,21 @@ class openram_test(unittest.TestCase): check = filecmp.cmp(filename1,filename2) if not check: debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2)) - f1 = open(filename1,"r") - s1 = f1.readlines().decode('utf-8') + f1 = open(filename1,mode="r",encoding='utf-8') + s1 = f1.readlines() f1.close() - f2 = open(filename2,"r").decode('utf-8') + f2 = open(filename2,mode="r",encoding='utf-8') s2 = f2.readlines() f2.close() mismatches=0 - for line in difflib.unified_diff(s1, s2): + for line in list(difflib.unified_diff(s1, s2)): mismatches += 1 - self.error("DIFF LINES:",line) - if mismatches>10: + if mismatches==0: + print("DIFF LINES:") + + if mismatches<11: + print(line.rstrip('\n')) + else: return False return False else: diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 91c52a90..1f0ffaab 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -30,7 +30,7 @@ if OPTS.check_lvsdrc and OPTS.tech_name == "freepdk45": debug.check(OPTS.drc_exe[0]!="magic","Magic does not support FreePDK45 for DRC.") if OPTS.drc_exe == None: - pass + from .none import run_drc,print_drc_stats elif "calibre"==OPTS.drc_exe[0]: from .calibre import run_drc,print_drc_stats elif "assura"==OPTS.drc_exe[0]: @@ -41,7 +41,7 @@ else: debug.warning("Did not find a supported DRC tool.") if OPTS.lvs_exe == None: - pass + from .none import run_lvs,print_lvs_stats elif "calibre"==OPTS.lvs_exe[0]: from .calibre import run_lvs,print_lvs_stats elif "assura"==OPTS.lvs_exe[0]: @@ -53,7 +53,7 @@ else: if OPTS.pex_exe == None: - pass + from .none import run_pex,print_pex_stats elif "calibre"==OPTS.pex_exe[0]: from .calibre import run_pex,print_pex_stats elif "magic"==OPTS.pex_exe[0]: diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 53e1e40c..0cb93582 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -99,7 +99,10 @@ def write_netgen_script(cell_name, sp_name): f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name)) # This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass # Is there a more elegant way to add this when needed? - f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_1}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_2}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_3}}\n".format(cell_name)) + f.write("flatten class {{{0}.spice precharge_array_4}}\n".format(cell_name)) f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name)) diff --git a/compiler/verify/none.py b/compiler/verify/none.py new file mode 100644 index 00000000..531a394d --- /dev/null +++ b/compiler/verify/none.py @@ -0,0 +1,41 @@ +""" +This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools. + +""" +import debug + +# Only print the warning once. +drc_warned = False +lvs_warned = False +pex_warned = False + +def run_drc(cell_name, gds_name, extract=False): + global drc_warned + if not drc_warned: + debug.warning("DRC unable to run.") + drc_warned=True + # Since we warned, return a failing test. + return 1 + +def run_lvs(cell_name, gds_name, sp_name, final_verification=False): + global lvs_warned + if not lvs_warned: + debug.warning("LVS unable to run.") + lvs_warned=True + # Since we warned, return a failing test. + return 1 + +def run_pex(name, gds_name, sp_name, output=None): + global pex_warned + if not pex_warned: + debug.warning("PEX unable to run.") + pex_warned=True + # Since we warned, return a failing test. + return 1 + +def print_drc_stats(): + pass +def print_lvs_stats(): + pass +def print_pex_stats(): + pass diff --git a/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log index bb655056..e9c97e12 100644 --- a/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 5.78125ns (ub: 5.9375 lb: 5.625) [characterizer.delay/analyze]: Min Period: 5.9375n with a delay of 3.1226964 / 0.30308602 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 16788.8 seconds GDS: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.gds ** GDS: 9.0 seconds diff --git a/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log b/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log index b758b31b..f1c4136a 100644 --- a/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log @@ -85,50 +85,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 1.953125ns (ub: 2.03125 lb: 1.875) [characterizer.delay/analyze]: Min Period: 2.03125n with a delay of 0.19175762 / 0.17403244 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 35039.9 seconds GDS: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.gds ** GDS: 5.3 seconds diff --git a/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log index c777cf84..98ec0b81 100644 --- a/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125) [characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1713644 / 0.19182711 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 8034.5 seconds GDS: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.gds ** GDS: 3.3 seconds diff --git a/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log index 7fbf2e95..92673b20 100644 --- a/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.265625ns (ub: 2.34375 lb: 2.1875) [characterizer.delay/analyze]: Min Period: 2.34375n with a delay of 1.2374402 / 0.25744693 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 12972.2 seconds GDS: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.gds ** GDS: 5.6 seconds diff --git a/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log index 27fa6d1d..f7645bc4 100644 --- a/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125) [characterizer.delay/analyze]: Min Period: 2.109375n with a delay of 1.1300259 / 0.13801474 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 4457.6 seconds GDS: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.gds ** GDS: 1.4 seconds diff --git a/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log index 310ab3e7..fbb51477 100644 --- a/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125) [characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1419594 / 0.15656674 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 5101.6 seconds GDS: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.gds ** GDS: 1.8 seconds diff --git a/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log index e1c8fa89..5ec76a8a 100644 --- a/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log @@ -82,50 +82,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 3.59375ns (ub: 3.75 lb: 3.4375) [characterizer.delay/analyze]: Min Period: 3.59375n with a delay of 1.850756 / 0.23319319 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 9948.6 seconds GDS: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.gds ** GDS: 5.9 seconds diff --git a/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log b/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log index c3816c2f..a9338950 100644 --- a/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log +++ b/lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 1.0546875ns (ub: 1.09375 lb: 1.015625) [characterizer.delay/analyze]: Min Period: 1.0546875n with a delay of 0.56986783 / 0.10418749 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414063 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414063 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0024414062 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.0036621094 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.014648437 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0024414062 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.0036621094 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.020751953 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.014648437 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.015869141 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.020751953 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.014648437 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.015869141 ** Characterization: 3369.3 seconds GDS: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.gds ** GDS: 0.8 seconds diff --git a/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log index f9ec88b7..e228495d 100644 --- a/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log @@ -86,50 +86,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 57.5ns (ub: 60.0 lb: 55.0) [characterizer.delay/analyze]: Min Period: 60.0n with a delay of 31.821678 / 3.9657764 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 13865.7 seconds GDS: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm.gds ** GDS: 9.5 seconds diff --git a/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log index 5f272478..aa01ded4 100644 --- a/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log @@ -86,50 +86,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25) [characterizer.delay/analyze]: Min Period: 17.5n with a delay of 9.657173 / 2.0055267 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 19670.7 seconds GDS: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm.gds ** GDS: 7.8 seconds diff --git a/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log index e7c734c8..4832f9c6 100644 --- a/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log @@ -86,50 +86,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 18.125ns (ub: 18.75 lb: 17.5) [characterizer.delay/analyze]: Min Period: 18.75n with a delay of 10.525582 / 2.331161 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 24789.5 seconds GDS: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm.gds ** GDS: 4.3 seconds diff --git a/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log index 5391de33..8744d09e 100644 --- a/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25) [characterizer.delay/analyze]: Min Period: 16.875n with a delay of 9.1997828 / 3.104732 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 10830.5 seconds GDS: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm.gds ** GDS: 5.3 seconds diff --git a/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log index 1ac5ebdd..f361c779 100644 --- a/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75) [characterizer.delay/analyze]: Min Period: 20.0n with a delay of 10.777462 / 1.9428786 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 3663.3 seconds GDS: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm.gds ** GDS: 1.2 seconds diff --git a/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log index c74dead5..61ce1268 100644 --- a/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log @@ -84,50 +84,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75) [characterizer.delay/analyze]: Min Period: 20.0n with a delay of 11.057892 / 2.1338514 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 4702.5 seconds GDS: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm.gds ** GDS: 2.1 seconds diff --git a/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log index 82344ea5..1c71e1d6 100644 --- a/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log @@ -85,50 +85,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 33.75ns (ub: 35.0 lb: 32.5) [characterizer.delay/analyze]: Min Period: 33.75n with a delay of 18.100242 / 3.0216206 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 9134.8 seconds GDS: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm.gds ** GDS: 5.1 seconds diff --git a/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log b/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log index 9b31bdda..91425053 100644 --- a/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log +++ b/lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log @@ -83,50 +83,50 @@ Trimming netlist to speed up characterization. [characterizer.delay/find_min_period]: MinPeriod Search: 9.0625ns (ub: 9.375 lb: 8.75) [characterizer.delay/analyze]: Min Period: 9.0625n with a delay of 5.0024145 / 1.5312283 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.052490234 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.052490234 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.075683594 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.0390625 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: -0.0036621094 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.05859375 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.075683594 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.0390625 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: -0.0036621094 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.05859375 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4 -[characterizer.setup_hold/analyze]: Setup Time for low_to_high transistion: 0.14892578 -[characterizer.setup_hold/analyze]: Setup Time for high_to_low transistion: 0.026855469 -[characterizer.setup_hold/analyze]: Hold Time for low_to_high transistion: 0.0085449219 -[characterizer.setup_hold/analyze]: Hold Time for high_to_low transistion: -0.13183594 +[characterizer.setup_hold/analyze]: Setup Time for low_to_high transition: 0.14892578 +[characterizer.setup_hold/analyze]: Setup Time for high_to_low transition: 0.026855469 +[characterizer.setup_hold/analyze]: Hold Time for low_to_high transition: 0.0085449219 +[characterizer.setup_hold/analyze]: Hold Time for high_to_low transition: -0.13183594 ** Characterization: 2269.5 seconds GDS: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm.gds ** GDS: 0.6 seconds diff --git a/technology/freepdk45/gds_lib/ms_flop.gds b/technology/freepdk45/gds_lib/ms_flop.gds deleted file mode 100644 index f1985551..00000000 Binary files a/technology/freepdk45/gds_lib/ms_flop.gds and /dev/null differ diff --git a/technology/freepdk45/sp_lib/ms_flop.sp b/technology/freepdk45/sp_lib/ms_flop.sp deleted file mode 100644 index 03016e5d..00000000 --- a/technology/freepdk45/sp_lib/ms_flop.sp +++ /dev/null @@ -1,29 +0,0 @@ -*master-slave flip-flop with both output and inverted ouput - -.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd -*clk inverter -mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNff1 clk_bar clk gnd gnd NMOS_VTG W=90n L=50n m=1 - -*transmission gate 1 -mtmP1 din clk int1 vdd PMOS_VTG W=180.0n L=50n m=1 -mtmN1 din clk_bar int1 gnd NMOS_VTG W=90n L=50n m=1 - -*foward inverter -mPff3 dout_bar int1 vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNff3 dout_bar int1 gnd gnd NMOS_VTG W=90n L=50n m=1 - -*backward inverter -mPff4 dout dout_bar vdd vdd PMOS_VTG W=180.0n L=50n m=1 -mNf4 dout dout_bar gnd gnd NMOS_VTG W=90n L=50n m=1 - -*transmission gate 2 -mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1 -mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1 -.ENDS dlatch - -.SUBCKT ms_flop din dout dout_bar clk vdd gnd -xmaster din mout mout_bar clk clk_bar vdd gnd dlatch -xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch -.ENDS flop - diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 3c28fab5..74bef19c 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -298,11 +298,11 @@ spice["msflop_leakage"] = 1 # Leakage power of flop in nW spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF spice["default_event_rate"] = 100 # Default event activity of every gate. MHz -spice["flop_transisition_prob"] = .5 # Transition probability of inverter. -spice["inv_transisition_prob"] = .5 # Transition probability of inverter. -spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand. -spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand. -spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor. +spice["flop_transition_prob"] = .5 # Transition probability of inverter. +spice["inv_transition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. ################################################### ##END Spice Simulation Parameters diff --git a/technology/scn3me_subm/mag_lib/.magicrc b/technology/scn3me_subm/mag_lib/.magicrc index d6068ec3..f52d0592 100644 --- a/technology/scn3me_subm/mag_lib/.magicrc +++ b/technology/scn3me_subm/mag_lib/.magicrc @@ -1,2 +1,5 @@ path sys +$::env(OPENRAM_TECH)/scn3me_subm/tech -tech load SCN3ME_SUBM.30 +tech load SCN3ME_SUBM.30 -noprompt +scalegrid 1 4 +set GND gnd +set VDD vdd diff --git a/technology/scn3me_subm/mag_lib/convertall.sh b/technology/scn3me_subm/mag_lib/convertall.sh new file mode 100755 index 00000000..f5e2482c --- /dev/null +++ b/technology/scn3me_subm/mag_lib/convertall.sh @@ -0,0 +1,14 @@ +magic -dnull -noconsole << EOF +load dff +gds write dff.gds +load cell_6t +gds write cell_6t.gds +load replica_cell_6t +gds write replica_cell_6t.gds +load sense_amp +gds write sense_amp.gds +load tri_gate +gds write tri_gate.gds +load write_driver +gds write write_driver.gds +EOF diff --git a/technology/scn3me_subm/sp_lib/dff.sp b/technology/scn3me_subm/sp_lib/dff.sp index 61515ab6..d3fa7635 100644 --- a/technology/scn3me_subm/sp_lib/dff.sp +++ b/technology/scn3me_subm/sp_lib/dff.sp @@ -1,47 +1,27 @@ +*********************** "dff" ****************************** * Positive edge-triggered FF -.subckt dff D Q clk vdd gnd +.SUBCKT dff D Q clk vdd gnd M0 vdd clk a_2_6# vdd p w=12u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M1 a_17_74# D vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M9 vdd Q a_76_84# vdd p w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M10 gnd clk a_2_6# gnd n w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M11 Q a_66_6# vdd vdd p w=12u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M12 a_17_6# D gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M20 gnd Q a_76_6# gnd n w=3u l=0.6u -+ ad=0p pd=0u as=0p ps=0u M21 Q a_66_6# gnd gnd n w=6u l=0.6u -+ ad=0p pd=0u as=0p ps=0u -.ends dff + +.ENDS dff diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index a3f51604..e6bf6da1 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -50,17 +50,18 @@ layer["blockage"] = 83 ################################################### ##DRC/LVS Rules Setup ################################################### +_lambda_ = 0.3 #technology parameter parameter={} -parameter["min_tx_size"] = 1.2 +parameter["min_tx_size"] = 4*_lambda_ parameter["beta"] = 2 drclvs_home=os.environ.get("DRCLVS_HOME") drc={} #grid size is 1/2 a lambda -drc["grid"]=0.15 +drc["grid"]=0.5*_lambda_ #DRC/LVS test set_up drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" @@ -68,52 +69,52 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" # minwidth_tx with contact (no dog bone transistors) -drc["minwidth_tx"] = 1.2 -drc["minlength_channel"] = 0.6 +drc["minwidth_tx"] = 4*_lambda_ +drc["minlength_channel"] = 2*_lambda_ # 1.3 Minimum spacing between wells of same type (if both are drawn) -drc["well_to_well"] = 1.8 +drc["well_to_well"] = 6*_lambda_ # 1.4 Minimum spacing between wells of different type (if both are drawn) drc["pwell_to_nwell"] = 0 # 1.1 Minimum width -drc["minwidth_well"] = 3.6 +drc["minwidth_well"] = 12*_lambda_ # 3.1 Minimum width -drc["minwidth_poly"] = 0.6 +drc["minwidth_poly"] = 2*_lambda_ # 3.2 Minimum spacing over active -drc["poly_to_poly"] = 0.9 +drc["poly_to_poly"] = 3*_lambda_ # 3.3 Minimum gate extension of active -drc["poly_extend_active"] = 0.6 +drc["poly_extend_active"] = 2*_lambda_ # 5.5.b Minimum spacing between poly contact and other poly (alternative rules) -drc["poly_to_polycontact"] = 1.2 +drc["poly_to_polycontact"] = 4*_lambda_ # ?? drc["active_enclosure_gate"] = 0.0 # 3.5 Minimum field poly to active -drc["poly_to_active"] = 0.3 +drc["poly_to_active"] = _lambda_ # 3.2.a Minimum spacing over field poly -drc["poly_to_field_poly"] = 0.9 +drc["poly_to_field_poly"] = 3*_lambda_ # Not a rule drc["minarea_poly"] = 0.0 # ?? -drc["active_to_body_active"] = 1.2 # Fix me +drc["active_to_body_active"] = 4*_lambda_ # Fix me # 2.1 Minimum width -drc["minwidth_active"] = 0.9 +drc["minwidth_active"] = 3*_lambda_ # 2.2 Minimum spacing -drc["active_to_active"] = 0.9 +drc["active_to_active"] = 3*_lambda_ # 2.3 Source/drain active to well edge -drc["well_enclosure_active"] = 1.8 +drc["well_enclosure_active"] = 6*_lambda_ # Reserved for asymmetric enclosures -drc["well_extend_active"] = 1.8 +drc["well_extend_active"] = 6*_lambda_ # Not a rule drc["minarea_active"] = 0.0 # 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width -drc["implant_to_channel"] = 0.9 +drc["implant_to_channel"] = 3*_lambda_ # 4.2 Minimum select overlap of active -drc["implant_enclosure_active"] = 0.6 +drc["implant_enclosure_active"] = 2*_lambda_ # 4.3 Minimum select overlap of contact -drc["implant_enclosure_contact"] = 0.3 +drc["implant_enclosure_contact"] = _lambda_ # Not a rule drc["implant_to_contact"] = 0 # Not a rule @@ -122,70 +123,70 @@ drc["implant_to_implant"] = 0 drc["minwidth_implant"] = 0 # 6.1 Exact contact size -drc["minwidth_contact"] = 0.6 +drc["minwidth_contact"] = 2*_lambda_ # 5.3 Minimum contact spacing -drc["contact_to_contact"] = 0.9 +drc["contact_to_contact"] = 3*_lambda_ # 6.2.b Minimum active overlap -drc["active_enclosure_contact"] = 0.3 +drc["active_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["active_extend_contact"] = 0.3 +drc["active_extend_contact"] = _lambda_ # 5.2.b Minimum poly overlap -drc["poly_enclosure_contact"] = 0.3 +drc["poly_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosures -drc["poly_extend_contact"] = 0.3 +drc["poly_extend_contact"] = _lambda_ # Reserved for other technologies -drc["contact_to_gate"] = 0.6 +drc["contact_to_gate"] = 2*_lambda_ # 5.4 Minimum spacing to gate of transistor -drc["contact_to_poly"] = 0.6 +drc["contact_to_poly"] = 2*_lambda_ # 7.1 Minimum width -drc["minwidth_metal1"] = 0.9 +drc["minwidth_metal1"] = 3*_lambda_ # 7.2 Minimum spacing -drc["metal1_to_metal1"] = 0.9 +drc["metal1_to_metal1"] = 3*_lambda_ # 7.3 Minimum overlap of any contact -drc["metal1_enclosure_contact"] = 0.3 +drc["metal1_enclosure_contact"] = _lambda_ # Reserved for asymmetric enclosure -drc["metal1_extend_contact"] = 0.3 +drc["metal1_extend_contact"] = _lambda_ # 8.3 Minimum overlap by metal1 -drc["metal1_enclosure_via1"] = 0.3 +drc["metal1_enclosure_via1"] = _lambda_ # Reserve for asymmetric enclosures -drc["metal1_extend_via1"] = 0.3 +drc["metal1_extend_via1"] = _lambda_ # Not a rule drc["minarea_metal1"] = 0 # 8.1 Exact size -drc["minwidth_via1"] = 0.6 +drc["minwidth_via1"] = 2*_lambda_ # 8.2 Minimum via1 spacing -drc["via1_to_via1"] = 0.6 +drc["via1_to_via1"] = 3*_lambda_ # 9.1 Minimum width -drc["minwidth_metal2"] = 0.9 +drc["minwidth_metal2"] = 3*_lambda_ # 9.2 Minimum spacing -drc["metal2_to_metal2"] = 0.9 +drc["metal2_to_metal2"] = 3*_lambda_ # 9.3 Minimum overlap of via1 -drc["metal2_extend_via1"] = 0.3 +drc["metal2_extend_via1"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal2_enclosure_via1"] = 0.3 +drc["metal2_enclosure_via1"] = _lambda_ # 14.3 Minimum overlap by metal2 -drc["metal2_extend_via2"] = 0.3 +drc["metal2_extend_via2"] = _lambda_ # Reserved for asymmetric enclosures -drc["metal2_enclosure_via2"] = 0.3 +drc["metal2_enclosure_via2"] = _lambda_ # Not a rule drc["minarea_metal2"] = 0 -# 14.2 Exact size -drc["minwidth_via2"] = 0.6 +# 14.1 Exact size +drc["minwidth_via2"] = 2*_lambda_ # 14.2 Minimum spacing -drc["via2_to_via2"] = 0.9 +drc["via2_to_via2"] = 3*_lambda_ # 15.1 Minimum width -drc["minwidth_metal3"] = 1.5 +drc["minwidth_metal3"] = 5*_lambda_ # 15.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 0.9 +drc["metal3_to_metal3"] = 3*_lambda_ # 15.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = 0.6 +drc["metal3_extend_via2"] = 2*_lambda_ # Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = 0.6 +drc["metal3_enclosure_via2"] = 2*_lambda_ # Not a rule drc["minarea_metal3"] = 0 @@ -259,12 +260,12 @@ spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW spice["msflop_leakage"] = 1 # Leakage power of flop in nW spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF -spice["default_event_rate"] = 100 # Default event activity of every gate. MHz -spice["flop_transisition_prob"] = .5 # Transition probability of inverter. -spice["inv_transisition_prob"] = .5 # Transition probability of inverter. -spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand. -spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand. -spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor. +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transition_prob"] = .5 # Transition probability of inverter. +spice["inv_transition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. ################################################### ##END Spice Simulation Parameters ################################################### diff --git a/technology/scn4m_subm/gds_lib/cell_6t.gds b/technology/scn4m_subm/gds_lib/cell_6t.gds new file mode 100644 index 00000000..df644048 Binary files /dev/null and b/technology/scn4m_subm/gds_lib/cell_6t.gds differ diff --git a/technology/scn4m_subm/gds_lib/dff.gds b/technology/scn4m_subm/gds_lib/dff.gds new file mode 100644 index 00000000..7825c3bc Binary files /dev/null and b/technology/scn4m_subm/gds_lib/dff.gds differ diff --git a/technology/scn4m_subm/gds_lib/replica_cell_6t.gds b/technology/scn4m_subm/gds_lib/replica_cell_6t.gds new file mode 100644 index 00000000..6a6b32ad Binary files /dev/null and b/technology/scn4m_subm/gds_lib/replica_cell_6t.gds differ diff --git a/technology/scn4m_subm/gds_lib/sense_amp.gds b/technology/scn4m_subm/gds_lib/sense_amp.gds new file mode 100644 index 00000000..cf5fa587 Binary files /dev/null and b/technology/scn4m_subm/gds_lib/sense_amp.gds differ diff --git a/technology/scn4m_subm/gds_lib/tri_gate.gds b/technology/scn4m_subm/gds_lib/tri_gate.gds new file mode 100644 index 00000000..ad83f4c6 Binary files /dev/null and b/technology/scn4m_subm/gds_lib/tri_gate.gds differ diff --git a/technology/scn4m_subm/gds_lib/write_driver.gds b/technology/scn4m_subm/gds_lib/write_driver.gds new file mode 100644 index 00000000..44dabaf1 Binary files /dev/null and b/technology/scn4m_subm/gds_lib/write_driver.gds differ diff --git a/technology/scn4m_subm/mag_lib/.magicrc b/technology/scn4m_subm/mag_lib/.magicrc new file mode 100644 index 00000000..0dfe42ef --- /dev/null +++ b/technology/scn4m_subm/mag_lib/.magicrc @@ -0,0 +1,5 @@ +path sys +$::env(OPENRAM_TECH)/scn4m_subm/tech +tech load SCN4M_SUBM.20 -noprompt +scalegrid 1 4 +set GND gnd +set VDD vdd diff --git a/technology/scn4m_subm/mag_lib/cell_6t.mag b/technology/scn4m_subm/mag_lib/cell_6t.mag new file mode 100644 index 00000000..f2e9906a --- /dev/null +++ b/technology/scn4m_subm/mag_lib/cell_6t.mag @@ -0,0 +1,117 @@ +magic +tech scmos +timestamp 1536091415 +<< nwell >> +rect -8 29 42 51 +<< pwell >> +rect -8 -8 42 29 +<< ntransistor >> +rect 7 10 9 18 +rect 29 10 31 18 +rect 10 3 14 5 +rect 24 3 28 5 +<< ptransistor >> +rect 7 37 11 40 +rect 27 37 31 40 +<< ndiffusion >> +rect -2 16 7 18 +rect 2 12 7 16 +rect -2 10 7 12 +rect 9 14 10 18 +rect 9 10 14 14 +rect 28 14 29 18 +rect 24 10 29 14 +rect 31 16 36 18 +rect 31 12 32 16 +rect 31 10 36 12 +rect 10 5 14 10 +rect 24 5 28 10 +rect 10 2 14 3 +rect 24 2 28 3 +<< pdiffusion >> +rect 2 37 7 40 +rect 11 37 12 40 +rect 26 37 27 40 +rect 31 37 32 40 +<< ndcontact >> +rect -2 12 2 16 +rect 10 14 14 18 +rect 24 14 28 18 +rect 32 12 36 16 +rect 10 -2 14 2 +rect 24 -2 28 2 +<< pdcontact >> +rect -2 36 2 40 +rect 12 36 16 40 +rect 22 36 26 40 +rect 32 36 36 40 +<< psubstratepcontact >> +rect -2 22 2 26 +rect 32 22 36 26 +<< nsubstratencontact >> +rect 32 44 36 48 +<< polysilicon >> +rect 7 40 11 42 +rect 27 40 31 42 +rect 7 35 11 37 +rect 7 21 9 35 +rect 27 34 31 37 +rect 15 33 31 34 +rect 19 32 31 33 +rect 7 20 21 21 +rect 7 19 24 20 +rect 7 18 9 19 +rect 29 18 31 32 +rect 7 8 9 10 +rect 17 5 21 6 +rect 29 8 31 10 +rect -2 3 10 5 +rect 14 3 24 5 +rect 28 3 36 5 +<< polycontact >> +rect 15 29 19 33 +rect 21 20 25 24 +rect 17 6 21 10 +<< metal1 >> +rect -2 44 15 48 +rect 19 44 32 48 +rect -2 40 2 44 +rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 26 2 29 +rect -2 16 2 22 +rect 11 18 15 36 +rect 23 24 27 36 +rect 25 20 27 24 +rect 14 14 15 18 +rect 23 18 27 20 +rect 32 26 36 29 +rect 23 14 24 18 +rect 32 16 36 22 +rect -2 6 17 9 +rect 21 6 36 9 +rect -2 5 36 6 +<< m2contact >> +rect 15 44 19 48 +rect -2 29 2 33 +rect 32 29 36 33 +rect 6 -2 10 2 +rect 20 -2 24 2 +<< metal2 >> +rect -2 33 2 48 +rect -2 -2 2 29 +rect 6 2 10 48 +rect 24 -2 28 48 +rect 32 33 36 48 +rect 32 -2 36 29 +<< bb >> +rect 0 0 34 46 +<< labels >> +rlabel metal2 0 0 0 0 1 gnd +rlabel metal2 34 0 34 0 1 gnd +rlabel m2contact 17 46 17 46 5 vdd +rlabel metal2 8 43 8 43 1 bl +rlabel metal2 26 43 26 43 1 br +rlabel metal1 4 7 4 7 1 wl +<< end >> diff --git a/technology/scn4m_subm/mag_lib/convertall.sh b/technology/scn4m_subm/mag_lib/convertall.sh new file mode 100755 index 00000000..f5e2482c --- /dev/null +++ b/technology/scn4m_subm/mag_lib/convertall.sh @@ -0,0 +1,14 @@ +magic -dnull -noconsole << EOF +load dff +gds write dff.gds +load cell_6t +gds write cell_6t.gds +load replica_cell_6t +gds write replica_cell_6t.gds +load sense_amp +gds write sense_amp.gds +load tri_gate +gds write tri_gate.gds +load write_driver +gds write write_driver.gds +EOF diff --git a/technology/scn4m_subm/mag_lib/dff.mag b/technology/scn4m_subm/mag_lib/dff.mag new file mode 100644 index 00000000..46d22c84 --- /dev/null +++ b/technology/scn4m_subm/mag_lib/dff.mag @@ -0,0 +1,279 @@ +magic +tech scmos +timestamp 1536089597 +<< nwell >> +rect 0 48 109 103 +<< pwell >> +rect 0 -3 109 48 +<< ntransistor >> +rect 11 6 13 26 +rect 19 6 21 16 +rect 24 6 26 16 +rect 33 6 35 16 +rect 38 6 40 16 +rect 47 6 49 16 +rect 63 6 65 16 +rect 68 6 70 16 +rect 78 6 80 16 +rect 83 6 85 16 +rect 91 6 93 26 +<< ptransistor >> +rect 11 54 13 94 +rect 19 74 21 94 +rect 25 74 27 94 +rect 33 74 35 94 +rect 39 74 41 94 +rect 47 74 49 94 +rect 63 74 65 94 +rect 68 74 70 94 +rect 78 84 80 94 +rect 83 84 85 94 +rect 91 54 93 94 +<< ndiffusion >> +rect 6 25 11 26 +rect 10 6 11 25 +rect 13 25 18 26 +rect 13 6 14 25 +rect 86 25 91 26 +rect 18 6 19 16 +rect 21 6 24 16 +rect 26 15 33 16 +rect 26 6 28 15 +rect 32 6 33 15 +rect 35 6 38 16 +rect 40 15 47 16 +rect 40 6 41 15 +rect 45 6 47 15 +rect 49 15 54 16 +rect 49 6 50 15 +rect 58 15 63 16 +rect 62 6 63 15 +rect 65 6 68 16 +rect 70 15 78 16 +rect 70 6 72 15 +rect 76 6 78 15 +rect 80 6 83 16 +rect 85 6 86 16 +rect 90 6 91 25 +rect 93 25 98 26 +rect 93 6 94 25 +<< pdiffusion >> +rect 6 93 11 94 +rect 10 54 11 93 +rect 13 55 14 94 +rect 18 74 19 94 +rect 21 74 25 94 +rect 27 93 33 94 +rect 27 74 28 93 +rect 32 74 33 93 +rect 35 74 39 94 +rect 41 93 47 94 +rect 41 74 42 93 +rect 46 74 47 93 +rect 49 93 54 94 +rect 49 74 50 93 +rect 58 93 63 94 +rect 62 74 63 93 +rect 65 74 68 94 +rect 70 93 78 94 +rect 70 74 72 93 +rect 76 84 78 93 +rect 80 84 83 94 +rect 85 93 91 94 +rect 85 84 86 93 +rect 76 74 77 84 +rect 13 54 18 55 +rect 90 54 91 93 +rect 93 93 98 94 +rect 93 54 94 93 +<< ndcontact >> +rect 6 6 10 25 +rect 14 6 18 25 +rect 28 6 32 15 +rect 41 6 45 15 +rect 50 6 54 15 +rect 58 6 62 15 +rect 72 6 76 15 +rect 86 6 90 25 +rect 94 6 98 25 +<< pdcontact >> +rect 6 54 10 93 +rect 14 55 18 94 +rect 28 74 32 93 +rect 42 74 46 93 +rect 50 74 54 93 +rect 58 74 62 93 +rect 72 74 76 93 +rect 86 54 90 93 +rect 94 54 98 93 +<< psubstratepcontact >> +rect 102 6 106 10 +<< nsubstratencontact >> +rect 102 89 106 93 +<< polysilicon >> +rect 11 94 13 96 +rect 19 94 21 96 +rect 25 94 27 96 +rect 33 94 35 96 +rect 39 94 41 96 +rect 47 94 49 96 +rect 63 94 65 96 +rect 68 94 70 96 +rect 78 94 80 96 +rect 83 94 85 96 +rect 91 94 93 96 +rect 11 37 13 54 +rect 19 46 21 74 +rect 11 26 13 33 +rect 19 16 21 42 +rect 25 38 27 74 +rect 33 54 35 74 +rect 33 29 35 50 +rect 24 27 35 29 +rect 39 71 41 74 +rect 24 16 26 27 +rect 39 23 41 67 +rect 47 61 49 74 +rect 63 73 65 74 +rect 54 71 65 73 +rect 34 19 35 23 +rect 33 16 35 19 +rect 38 19 39 23 +rect 38 16 40 19 +rect 47 16 49 57 +rect 53 19 55 67 +rect 68 63 70 74 +rect 78 67 80 84 +rect 76 65 80 67 +rect 63 61 70 63 +rect 61 24 63 33 +rect 68 31 70 61 +rect 83 53 85 84 +rect 79 51 85 53 +rect 78 31 80 47 +rect 91 45 93 54 +rect 89 41 93 45 +rect 68 29 75 31 +rect 61 22 70 24 +rect 53 17 65 19 +rect 63 16 65 17 +rect 68 16 70 22 +rect 73 19 75 29 +rect 78 27 79 31 +rect 73 17 80 19 +rect 78 16 80 17 +rect 83 16 85 31 +rect 91 26 93 41 +rect 11 4 13 6 +rect 19 4 21 6 +rect 24 4 26 6 +rect 33 4 35 6 +rect 38 4 40 6 +rect 47 4 49 6 +rect 63 4 65 6 +rect 68 4 70 6 +rect 78 4 80 6 +rect 83 4 85 6 +rect 91 4 93 6 +<< polycontact >> +rect 17 42 21 46 +rect 10 33 14 37 +rect 31 50 35 54 +rect 25 34 29 38 +rect 39 67 43 71 +rect 45 57 49 61 +rect 30 19 34 23 +rect 39 19 43 23 +rect 53 67 57 71 +rect 59 59 63 63 +rect 74 61 78 65 +rect 59 33 63 37 +rect 77 47 81 51 +rect 85 41 89 45 +rect 79 27 83 31 +<< metal1 >> +rect 0 97 109 103 +rect 14 94 18 97 +rect 6 93 10 94 +rect 28 93 32 94 +rect 22 74 28 77 +rect 42 93 46 97 +rect 50 93 54 94 +rect 58 93 62 97 +rect 71 93 77 94 +rect 71 74 72 93 +rect 76 74 77 93 +rect 86 93 90 97 +rect 50 71 53 74 +rect 43 68 53 71 +rect 26 57 45 60 +rect 52 60 59 63 +rect 52 54 55 60 +rect 71 56 74 65 +rect 10 50 31 52 +rect 35 51 55 54 +rect 62 53 74 56 +rect 94 93 98 94 +rect 102 93 106 97 +rect 6 49 34 50 +rect 21 43 38 46 +rect 18 34 25 37 +rect 62 37 65 53 +rect 94 51 98 54 +rect 81 48 94 51 +rect 74 41 85 44 +rect 29 34 59 37 +rect 6 25 10 26 +rect 14 25 18 26 +rect 31 23 34 34 +rect 63 34 65 37 +rect 94 31 98 47 +rect 83 28 98 31 +rect 94 25 98 28 +rect 43 19 53 22 +rect 50 16 53 19 +rect 22 15 32 16 +rect 22 13 28 15 +rect 41 15 46 16 +rect 45 6 46 15 +rect 50 15 54 16 +rect 58 15 62 16 +rect 70 15 77 16 +rect 70 13 72 15 +rect 71 6 72 13 +rect 76 6 77 15 +rect 14 3 18 6 +rect 41 3 46 6 +rect 58 3 62 6 +rect 86 3 90 6 +rect 102 3 106 6 +rect 0 -3 109 3 +<< m2contact >> +rect 22 70 26 74 +rect 70 70 74 74 +rect 22 57 26 61 +rect 6 50 10 54 +rect 38 43 42 47 +rect 14 33 18 37 +rect 94 47 98 51 +rect 70 40 74 44 +rect 6 26 10 30 +rect 22 16 26 20 +rect 70 16 74 20 +<< metal2 >> +rect 22 61 26 70 +rect 6 30 10 50 +rect 22 20 26 57 +rect 70 44 74 70 +rect 70 20 74 40 +<< bb >> +rect 0 0 109 100 +<< labels >> +rlabel m2contact 15 34 15 34 4 clk +rlabel m2contact 40 45 40 45 4 D +rlabel m2contact 96 49 96 49 4 Q +rlabel metal1 32 98 32 98 4 vdd +rlabel metal1 44 1 44 1 4 gnd +<< properties >> +string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000 +<< end >> diff --git a/technology/scn4m_subm/mag_lib/replica_cell_6t.mag b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag new file mode 100644 index 00000000..d0dc472f --- /dev/null +++ b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag @@ -0,0 +1,118 @@ +magic +tech scmos +timestamp 1536091380 +<< nwell >> +rect -8 29 42 51 +<< pwell >> +rect -8 -8 42 29 +<< ntransistor >> +rect 7 10 9 18 +rect 29 10 31 18 +rect 10 3 14 5 +rect 24 3 28 5 +<< ptransistor >> +rect 7 37 11 40 +rect 27 37 31 40 +<< ndiffusion >> +rect -2 16 7 18 +rect 2 12 7 16 +rect -2 10 7 12 +rect 9 14 10 18 +rect 9 10 14 14 +rect 28 14 29 18 +rect 24 10 29 14 +rect 31 16 36 18 +rect 31 12 32 16 +rect 31 10 36 12 +rect 10 5 14 10 +rect 24 5 28 10 +rect 10 2 14 3 +rect 24 2 28 3 +<< pdiffusion >> +rect 2 37 7 40 +rect 11 37 12 40 +rect 26 37 27 40 +rect 31 37 32 40 +<< ndcontact >> +rect -2 12 2 16 +rect 10 14 14 18 +rect 24 14 28 18 +rect 32 12 36 16 +rect 10 -2 14 2 +rect 24 -2 28 2 +<< pdcontact >> +rect -2 36 2 40 +rect 12 36 16 40 +rect 22 36 26 40 +rect 32 36 36 40 +<< psubstratepcontact >> +rect -2 22 2 26 +rect 32 22 36 26 +<< nsubstratencontact >> +rect 32 44 36 48 +<< polysilicon >> +rect 7 40 11 42 +rect 27 40 31 42 +rect 7 35 11 37 +rect 7 21 9 35 +rect 27 34 31 37 +rect 15 33 31 34 +rect 19 32 31 33 +rect 7 20 21 21 +rect 7 19 24 20 +rect 7 18 9 19 +rect 29 18 31 32 +rect 7 8 9 10 +rect 17 5 21 6 +rect 29 8 31 10 +rect -2 3 10 5 +rect 14 3 24 5 +rect 28 3 36 5 +<< polycontact >> +rect 15 29 19 33 +rect 21 20 25 24 +rect 17 6 21 10 +<< metal1 >> +rect -2 44 15 48 +rect 19 44 32 48 +rect -2 40 2 44 +rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 26 2 29 +rect 11 22 15 36 +rect 23 24 27 36 +rect -2 18 15 22 +rect 25 20 27 24 +rect -2 16 2 18 +rect 14 14 15 18 +rect 23 18 27 20 +rect 32 26 36 29 +rect 23 14 24 18 +rect 32 16 36 22 +rect -2 6 17 9 +rect 21 6 36 9 +rect -2 5 36 6 +<< m2contact >> +rect 15 44 19 48 +rect -2 29 2 33 +rect 32 29 36 33 +rect 6 -2 10 2 +rect 20 -2 24 2 +<< metal2 >> +rect -2 33 2 48 +rect -2 -2 2 29 +rect 6 2 10 48 +rect 24 -2 28 48 +rect 32 33 36 48 +rect 32 -2 36 29 +<< bb >> +rect 0 0 34 46 +<< labels >> +rlabel metal2 0 0 0 0 1 gnd +rlabel metal2 34 0 34 0 1 gnd +rlabel m2contact 17 46 17 46 5 vdd +rlabel metal2 8 43 8 43 1 bl +rlabel metal2 26 43 26 43 1 br +rlabel metal1 4 7 4 7 1 wl +<< end >> diff --git a/technology/scn4m_subm/mag_lib/sense_amp.mag b/technology/scn4m_subm/mag_lib/sense_amp.mag new file mode 100644 index 00000000..e5fa4373 --- /dev/null +++ b/technology/scn4m_subm/mag_lib/sense_amp.mag @@ -0,0 +1,136 @@ +magic +tech scmos +timestamp 1536089670 +<< nwell >> +rect 0 0 40 102 +<< pwell >> +rect 0 102 40 163 +<< ntransistor >> +rect 21 130 23 139 +rect 12 108 14 117 +rect 20 108 22 117 +<< ptransistor >> +rect 12 78 14 96 +rect 20 78 22 96 +rect 11 20 13 44 +rect 27 20 29 44 +<< ndiffusion >> +rect 20 130 21 139 +rect 23 130 24 139 +rect 11 108 12 117 +rect 14 108 15 117 +rect 19 108 20 117 +rect 22 108 23 117 +<< pdiffusion >> +rect 7 94 12 96 +rect 11 80 12 94 +rect 7 78 12 80 +rect 14 94 20 96 +rect 14 80 15 94 +rect 19 80 20 94 +rect 14 78 20 80 +rect 22 94 27 96 +rect 22 80 23 94 +rect 22 78 27 80 +rect 10 20 11 44 +rect 13 20 14 44 +rect 26 20 27 44 +rect 29 20 30 44 +<< ndcontact >> +rect 16 130 20 139 +rect 24 130 28 139 +rect 7 108 11 117 +rect 15 108 19 117 +rect 23 108 27 117 +<< pdcontact >> +rect 7 80 11 94 +rect 15 80 19 94 +rect 23 80 27 94 +rect 6 20 10 44 +rect 14 20 18 44 +rect 22 20 26 44 +rect 30 20 34 44 +<< psubstratepcontact >> +rect 32 137 36 141 +<< nsubstratencontact >> +rect 27 70 31 74 +<< polysilicon >> +rect 21 139 23 149 +rect 21 129 23 130 +rect 3 127 23 129 +rect 3 47 5 127 +rect 12 122 34 124 +rect 12 117 14 122 +rect 20 117 22 119 +rect 12 96 14 108 +rect 20 96 22 108 +rect 32 105 34 122 +rect 30 101 34 105 +rect 12 76 14 78 +rect 20 69 22 78 +rect 13 67 22 69 +rect 9 55 11 65 +rect 32 55 34 101 +rect 33 51 34 55 +rect 3 45 13 47 +rect 11 44 13 45 +rect 27 44 29 46 +rect 11 19 13 20 +rect 27 19 29 20 +rect 11 17 29 19 +<< polycontact >> +rect 20 149 24 153 +rect 26 101 30 105 +rect 9 65 13 69 +rect 9 51 13 55 +rect 29 51 33 55 +<< metal1 >> +rect -2 149 20 153 +rect 24 149 36 153 +rect 28 133 32 137 +rect 16 117 19 130 +rect 7 94 11 108 +rect 23 105 27 108 +rect 23 101 26 105 +rect 7 69 11 80 +rect 15 94 19 96 +rect 15 78 19 80 +rect 23 94 27 101 +rect 23 78 27 80 +rect 15 75 18 78 +rect 15 74 31 75 +rect 15 72 27 74 +rect 7 65 9 69 +rect 6 44 9 54 +rect 33 51 34 55 +rect 31 44 34 51 +rect 3 20 6 23 +rect 3 15 7 20 +<< m2contact >> +rect 32 133 36 137 +rect 27 66 31 70 +rect 13 44 17 48 +rect 22 44 26 48 +rect 3 11 7 15 +<< metal2 >> +rect 10 48 14 163 +rect 20 48 24 163 +rect 32 129 36 133 +rect 27 62 31 66 +rect 10 44 13 48 +rect 20 44 22 48 +rect 3 0 7 11 +rect 10 0 14 44 +rect 20 0 24 44 +<< bb >> +rect 0 0 34 163 +<< labels >> +flabel metal1 0 149 0 149 4 FreeSans 26 0 0 0 en +rlabel metal2 34 131 34 131 1 gnd +rlabel metal2 29 64 29 64 1 vdd +rlabel metal2 12 161 12 161 5 bl +rlabel metal2 22 161 22 161 5 br +rlabel metal2 5 3 5 3 1 dout +<< properties >> +string path 270.000 468.000 270.000 486.000 288.000 486.000 288.000 468.000 270.000 468.000 +<< end >> diff --git a/technology/scn4m_subm/mag_lib/tri_gate.mag b/technology/scn4m_subm/mag_lib/tri_gate.mag new file mode 100644 index 00000000..bda635c7 --- /dev/null +++ b/technology/scn4m_subm/mag_lib/tri_gate.mag @@ -0,0 +1,98 @@ +magic +tech scmos +timestamp 1536089695 +<< nwell >> +rect -2 45 38 73 +<< pwell >> +rect -2 0 38 45 +<< ntransistor >> +rect 9 27 11 31 +rect 17 27 19 31 +rect 25 27 27 31 +<< ptransistor >> +rect 9 53 11 61 +rect 17 53 19 61 +rect 25 53 27 61 +<< ndiffusion >> +rect 8 27 9 31 +rect 11 27 12 31 +rect 16 27 17 31 +rect 19 27 20 31 +rect 24 27 25 31 +rect 27 27 28 31 +<< pdiffusion >> +rect 8 53 9 61 +rect 11 53 12 61 +rect 16 53 17 61 +rect 19 53 20 61 +rect 24 53 25 61 +rect 27 53 28 61 +<< ndcontact >> +rect 4 27 8 31 +rect 12 27 16 31 +rect 20 27 24 31 +rect 28 27 32 31 +<< pdcontact >> +rect 4 53 8 61 +rect 12 53 16 61 +rect 20 53 24 61 +rect 28 53 32 61 +<< psubstratepcontact >> +rect 12 19 16 23 +<< nsubstratencontact >> +rect 12 65 16 69 +<< polysilicon >> +rect 25 63 35 65 +rect 9 61 11 63 +rect 17 61 19 63 +rect 25 61 27 63 +rect 9 50 11 53 +rect 9 31 11 46 +rect 17 42 19 53 +rect 25 51 27 53 +rect 17 31 19 38 +rect 25 31 27 33 +rect 9 25 11 27 +rect 17 25 19 27 +rect 25 16 27 27 +rect 33 8 35 63 +rect 32 6 35 8 +<< polycontact >> +rect 9 46 13 50 +rect 16 38 20 42 +rect 25 12 29 16 +rect 28 4 32 8 +<< metal1 >> +rect 16 65 23 69 +rect 12 61 16 65 +rect 3 53 4 61 +rect 3 42 6 53 +rect 13 46 15 50 +rect 3 38 16 42 +rect 3 31 6 38 +rect 29 31 32 53 +rect 3 27 4 31 +rect 12 23 16 27 +rect 16 19 24 23 +rect 0 12 25 16 +rect 29 12 36 16 +rect 0 4 28 8 +rect 32 4 36 8 +<< m2contact >> +rect 23 65 27 69 +rect 15 46 19 50 +rect 25 34 29 38 +rect 24 19 28 23 +<< metal2 >> +rect 15 34 25 38 +rect 15 0 19 34 +<< bb >> +rect 0 0 34 73 +<< labels >> +rlabel metal1 0 12 0 12 3 en +rlabel metal1 0 4 0 4 2 en_bar +rlabel metal2 16 1 16 1 1 out +rlabel m2contact 26 21 26 21 1 gnd +rlabel m2contact 25 67 25 67 1 vdd +rlabel m2contact 17 48 17 48 1 in +<< end >> diff --git a/technology/scn4m_subm/mag_lib/write_driver.mag b/technology/scn4m_subm/mag_lib/write_driver.mag new file mode 100644 index 00000000..ab2014aa --- /dev/null +++ b/technology/scn4m_subm/mag_lib/write_driver.mag @@ -0,0 +1,224 @@ +magic +tech scmos +timestamp 1536089714 +<< nwell >> +rect -3 101 37 138 +rect -3 0 37 51 +<< pwell >> +rect -3 138 37 202 +rect -3 51 37 101 +<< ntransistor >> +rect 9 177 11 189 +rect 17 177 19 189 +rect 15 162 27 164 +rect 9 144 11 148 +rect 17 144 19 148 +rect 10 82 12 89 +rect 18 82 20 89 +rect 8 57 10 64 +rect 16 57 18 64 +rect 24 60 26 64 +<< ptransistor >> +rect 9 125 11 132 +rect 17 125 19 132 +rect 10 107 12 114 +rect 18 107 20 114 +rect 8 38 10 45 +rect 16 38 18 45 +rect 24 38 26 45 +<< ndiffusion >> +rect 8 177 9 189 +rect 11 177 12 189 +rect 16 177 17 189 +rect 19 177 20 189 +rect 15 164 27 165 +rect 15 161 27 162 +rect 12 157 15 160 +rect 12 156 16 157 +rect 8 144 9 148 +rect 11 144 12 148 +rect 16 144 17 148 +rect 19 144 20 148 +rect 9 82 10 89 +rect 12 82 13 89 +rect 17 82 18 89 +rect 20 82 21 89 +rect 25 82 26 86 +rect 7 57 8 64 +rect 10 57 11 64 +rect 15 57 16 64 +rect 18 57 19 64 +rect 23 60 24 64 +rect 26 60 27 64 +<< pdiffusion >> +rect 8 125 9 132 +rect 11 125 12 132 +rect 16 125 17 132 +rect 19 125 20 132 +rect 12 122 16 125 +rect 9 107 10 114 +rect 12 107 13 114 +rect 17 107 18 114 +rect 20 107 21 114 +rect 7 38 8 45 +rect 10 38 11 45 +rect 15 38 16 45 +rect 18 38 19 45 +rect 23 38 24 45 +rect 26 38 27 45 +rect 3 35 7 38 +<< ndcontact >> +rect 4 177 8 189 +rect 12 177 16 189 +rect 20 177 24 189 +rect 15 165 27 169 +rect 15 157 27 161 +rect 4 144 8 148 +rect 12 144 16 148 +rect 20 144 24 148 +rect 5 82 9 89 +rect 13 82 17 89 +rect 21 82 25 89 +rect 3 57 7 64 +rect 11 57 15 64 +rect 19 57 23 64 +rect 27 60 31 64 +<< pdcontact >> +rect 4 125 8 132 +rect 12 125 16 132 +rect 20 125 24 132 +rect 5 107 9 114 +rect 13 107 17 114 +rect 21 107 25 114 +rect 3 38 7 45 +rect 11 38 15 45 +rect 19 38 23 45 +rect 27 38 31 45 +<< psubstratepcontact >> +rect 12 152 16 156 +rect 26 82 30 86 +<< nsubstratencontact >> +rect 12 118 16 122 +rect 3 31 7 35 +<< polysilicon >> +rect 9 194 30 196 +rect 9 189 11 194 +rect 17 189 19 191 +rect 28 185 30 194 +rect 9 175 11 177 +rect 17 172 19 177 +rect 6 170 19 172 +rect 6 167 8 170 +rect 13 162 15 164 +rect 27 162 33 164 +rect 9 148 11 150 +rect 17 148 19 150 +rect 9 132 11 144 +rect 17 132 19 144 +rect 9 124 11 125 +rect 2 122 11 124 +rect 17 124 19 125 +rect 17 122 28 124 +rect 2 75 4 122 +rect 10 114 12 116 +rect 18 114 20 116 +rect 10 89 12 107 +rect 18 106 20 107 +rect 16 104 20 106 +rect 16 92 18 104 +rect 26 100 28 122 +rect 27 96 28 100 +rect 16 90 20 92 +rect 18 89 20 90 +rect 10 81 12 82 +rect 10 79 13 81 +rect 2 71 3 75 +rect 11 71 13 79 +rect 18 79 20 82 +rect 18 77 23 79 +rect 31 71 33 162 +rect 11 69 33 71 +rect 11 67 13 69 +rect 8 65 13 67 +rect 8 64 10 65 +rect 16 64 18 66 +rect 24 64 26 66 +rect 8 45 10 57 +rect 16 52 18 57 +rect 24 52 26 60 +rect 16 50 26 52 +rect 16 45 18 50 +rect 24 45 26 50 +rect 8 28 10 38 +rect 16 14 18 38 +rect 24 36 26 38 +<< polycontact >> +rect 28 181 32 185 +rect 4 163 8 167 +rect 23 96 27 100 +rect 3 71 7 75 +rect 23 75 27 79 +rect 7 24 11 28 +rect 15 10 19 14 +<< metal1 >> +rect 5 192 10 196 +rect 5 189 8 192 +rect 32 181 33 185 +rect 13 169 16 177 +rect 13 165 15 169 +rect 4 148 8 163 +rect 12 157 15 161 +rect 12 156 16 157 +rect 12 148 16 152 +rect 4 132 8 144 +rect 20 142 24 144 +rect 30 142 33 181 +rect 20 138 33 142 +rect 20 132 24 138 +rect 12 122 16 125 +rect 13 114 17 118 +rect 5 104 9 107 +rect 21 104 25 107 +rect 5 101 25 104 +rect 5 89 9 101 +rect 21 100 25 101 +rect 21 96 23 100 +rect 25 82 26 90 +rect 4 64 7 71 +rect 27 64 31 79 +rect 3 51 7 57 +rect 3 48 15 51 +rect 11 45 15 48 +rect 27 45 31 60 +rect 3 35 7 38 +rect 19 35 23 38 +rect 7 31 19 35 +rect 0 24 7 28 +rect 11 24 36 28 +<< m2contact >> +rect 10 192 14 196 +rect 20 189 24 193 +rect 23 153 27 157 +rect 16 118 20 122 +rect 26 86 30 90 +rect 19 64 23 68 +rect 19 31 23 35 +rect 15 6 19 10 +<< metal2 >> +rect 10 196 14 202 +rect 20 193 24 202 +rect 20 177 24 189 +rect 15 0 19 6 +<< bb >> +rect 0 0 34 202 +<< labels >> +rlabel metal2 15 1 15 1 1 din +rlabel metal1 2 25 2 25 3 en +rlabel metal2 12 200 12 200 5 bl +rlabel metal2 22 200 22 200 5 br +rlabel m2contact 21 66 21 66 1 gnd +rlabel m2contact 28 88 28 88 1 gnd +rlabel m2contact 21 33 21 33 1 vdd +rlabel m2contact 18 120 18 120 1 vdd +rlabel m2contact 25 155 25 155 1 gnd +<< end >> diff --git a/technology/scn4m_subm/models/ff/nmos.sp b/technology/scn4m_subm/models/ff/nmos.sp new file mode 100644 index 00000000..07ca8dba --- /dev/null +++ b/technology/scn4m_subm/models/ff/nmos.sp @@ -0,0 +1,10 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0) + diff --git a/technology/scn4m_subm/models/ff/pmos.sp b/technology/scn4m_subm/models/ff/pmos.sp new file mode 100644 index 00000000..b4dc9026 --- /dev/null +++ b/technology/scn4m_subm/models/ff/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4m_subm/models/nom/nmos.sp b/technology/scn4m_subm/models/nom/nmos.sp new file mode 100644 index 00000000..ad4db2b8 --- /dev/null +++ b/technology/scn4m_subm/models/nom/nmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4m_subm/models/nom/pmos.sp b/technology/scn4m_subm/models/nom/pmos.sp new file mode 100644 index 00000000..9ecb13e1 --- /dev/null +++ b/technology/scn4m_subm/models/nom/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4m_subm/models/ss/nmos.sp b/technology/scn4m_subm/models/ss/nmos.sp new file mode 100644 index 00000000..3d9bda57 --- /dev/null +++ b/technology/scn4m_subm/models/ss/nmos.sp @@ -0,0 +1,10 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL n NMOS (LEVEL=49 VTHO=0.669845 ++ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0) + diff --git a/technology/scn4m_subm/models/ss/pmos.sp b/technology/scn4m_subm/models/ss/pmos.sp new file mode 100644 index 00000000..b4dc9026 --- /dev/null +++ b/technology/scn4m_subm/models/ss/pmos.sp @@ -0,0 +1,9 @@ +********************************************* +* Transistor Models +* Note: These models are approximate +* and should be substituted with actual +* models from MOSIS or SCN4ME +********************************************* + +.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 ++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn4m_subm/sp_lib/cell_6t.sp b/technology/scn4m_subm/sp_lib/cell_6t.sp new file mode 100644 index 00000000..846cc371 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/cell_6t.sp @@ -0,0 +1,13 @@ + +*********************** "cell_6t" ****************************** +.SUBCKT cell_6t bl br wl vdd gnd +* SPICE3 file created from cell_6t.ext - technology: scmos + +M1000 a_36_40# a_28_32# vdd vdd p w=0.6u l=0.8u +M1001 vdd a_36_40# a_28_32# vdd p w=0.6u l=0.8u +M1002 a_36_40# a_28_32# gnd gnd n w=1.6u l=0.4u +M1003 gnd a_36_40# a_28_32# gnd n w=1.6u l=0.4u +M1004 a_36_40# wl bl gnd n w=0.8u l=0.4u +M1005 a_28_32# wl br gnd n w=0.8u l=0.4u + +.ENDS diff --git a/technology/scn4m_subm/sp_lib/dff.sp b/technology/scn4m_subm/sp_lib/dff.sp new file mode 100644 index 00000000..3d8db9d8 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/dff.sp @@ -0,0 +1,30 @@ +*********************** "dff" ****************************** +* Positive edge-triggered FF +.SUBCKT dff D Q clk vdd gnd + +* SPICE3 file created from dff.ext - technology: scmos + +M1000 vdd clk a_24_24# vdd p w=8u l=0.4u +M1001 a_84_296# D vdd vdd p w=4u l=0.4u +M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u +M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u +M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u +M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u +M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u +M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u +M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u +M1009 vdd Q a_320_336# vdd p w=2u l=0.4u +M1010 gnd clk a_24_24# gnd n w=4u l=0.4u +M1011 Q a_280_24# vdd vdd p w=8u l=0.4u +M1012 a_84_24# D gnd gnd n w=2u l=0.4u +M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u +M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u +M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u +M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u +M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u +M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u +M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u +M1020 gnd Q a_320_24# gnd n w=2u l=0.4u +M1021 Q a_280_24# gnd gnd n w=4u l=0.4u + +.ENDS diff --git a/technology/scn4m_subm/sp_lib/replica_cell_6t.sp b/technology/scn4m_subm/sp_lib/replica_cell_6t.sp new file mode 100644 index 00000000..d26d600f --- /dev/null +++ b/technology/scn4m_subm/sp_lib/replica_cell_6t.sp @@ -0,0 +1,14 @@ + +*********************** "cell_6t" ****************************** +.SUBCKT replica_cell_6t bl br wl vdd gnd +* SPICE3 file created from replica_cell_6t.ext - technology: scmos + +M1000 gnd a_28_32# vdd vdd p w=0.6u l=0.8u +M1001 vdd gnd a_28_32# vdd p w=0.6u l=0.8u +** SOURCE/DRAIN TIED +M1002 gnd a_28_32# gnd gnd n w=1.6u l=0.4u +M1003 gnd gnd a_28_32# gnd n w=1.6u l=0.4u +M1004 gnd wl bl gnd n w=0.8u l=0.4u +M1005 a_28_32# wl br gnd n w=0.8u l=0.4u + +.ENDS diff --git a/technology/scn4m_subm/sp_lib/sense_amp.sp b/technology/scn4m_subm/sp_lib/sense_amp.sp new file mode 100644 index 00000000..70622413 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/sense_amp.sp @@ -0,0 +1,15 @@ +*********************** "sense_amp" ****************************** + +.SUBCKT sense_amp bl br dout en vdd gnd + +* SPICE3 file created from sense_amp.ext - technology: scmos + +M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u +M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u +M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u +M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u +M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u +M1005 bl en dout vdd p w=4.8u l=0.4u +M1006 a_48_304# en br vdd p w=4.8u l=0.4u + +.ENDS diff --git a/technology/scn4m_subm/sp_lib/tri_gate.sp b/technology/scn4m_subm/sp_lib/tri_gate.sp new file mode 100644 index 00000000..451feba3 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/tri_gate.sp @@ -0,0 +1,14 @@ +*********************** tri_gate ****************************** + +.SUBCKT tri_gate in out en en_bar vdd gnd + +* SPICE3 file created from tri_gate.ext - technology: scmos + +M1000 vdd in a_16_108# vdd p w=1.6u l=0.4u +M1001 a_76_212# a_16_108# vdd vdd p w=1.6u l=0.4u +M1002 out en_bar a_76_212# vdd p w=1.6u l=0.4u +M1003 gnd in a_16_108# gnd n w=0.8u l=0.4u +M1004 a_76_108# a_16_108# gnd gnd n w=0.8u l=0.4u +M1005 out en a_76_108# gnd n w=0.8u l=0.4u + +.ENDS diff --git a/technology/scn4m_subm/sp_lib/write_driver.sp b/technology/scn4m_subm/sp_lib/write_driver.sp new file mode 100644 index 00000000..afcf1049 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/write_driver.sp @@ -0,0 +1,23 @@ +*********************** Write_Driver ****************************** +.SUBCKT write_driver din bl br en vdd gnd +* SPICE3 file created from write_driver.ext - technology: scmos + +M1000 a_44_708# a_36_700# bl gnd n w=2.4u l=0.4u +M1001 br a_16_500# a_44_708# gnd n w=2.4u l=0.4u +M1002 a_44_708# en gnd gnd n w=2.4u l=0.4u +M1003 gnd a_8_284# a_16_500# gnd n w=0.8u l=0.4u +M1004 a_36_700# a_20_328# gnd gnd n w=0.8u l=0.4u +M1005 vdd a_8_284# a_16_500# vdd p w=1.4u l=0.4u +M1006 a_36_700# a_20_328# vdd vdd p w=1.4u l=0.4u +M1007 vdd en a_20_328# vdd p w=1.4u l=0.4u +M1008 a_20_328# a_64_360# vdd vdd p w=1.4u l=0.4u +M1009 a_48_328# en a_20_328# gnd n w=1.4u l=0.4u +M1010 gnd a_64_360# a_48_328# gnd n w=1.4u l=0.4u +M1011 a_40_228# en a_8_284# gnd n w=1.4u l=0.4u +M1012 gnd din a_40_228# gnd n w=1.4u l=0.4u +M1013 a_64_360# din gnd gnd n w=0.8u l=0.4u +M1014 a_8_284# en vdd vdd p w=1.4u l=0.4u +M1015 vdd din a_8_284# vdd p w=1.4u l=0.4u +M1016 a_64_360# din vdd vdd p w=1.4u l=0.4u + +.ENDS diff --git a/technology/scn4m_subm/sue_lib/cell_6t.sue b/technology/scn4m_subm/sue_lib/cell_6t.sue new file mode 100644 index 00000000..427b1d05 --- /dev/null +++ b/technology/scn4m_subm/sue_lib/cell_6t.sue @@ -0,0 +1,46 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_cell_6t {} { + make inout -name BL -origin {190 360} + make inout -name BR -origin {830 360} + make input -name WL -origin {240 120} + make global -orient RXY -name vdd -origin {520 160} + make global -name gnd -origin {510 600} + make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} + make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} + make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} + make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} + make nmos -W 2.4u -L 0.6u -origin {630 490} + make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} + make_wire 630 550 630 530 + make_wire 400 530 400 550 + make_wire 400 190 400 170 + make_wire 630 170 630 190 + make_wire 400 360 400 270 + make_wire 310 360 400 360 + make_wire 630 360 630 450 + make_wire 630 360 700 360 + make_wire 270 300 270 120 + make_wire 270 120 740 120 + make_wire 740 120 740 300 + make_wire 230 360 190 360 + make_wire 780 360 830 360 + make_wire 510 550 400 550 + make_wire 510 550 630 550 + make_wire 510 550 510 600 + make_wire 520 170 400 170 + make_wire 520 170 630 170 + make_wire 520 160 520 170 + make_wire 240 120 270 120 + make_wire 460 290 630 290 + make_wire 460 290 460 490 + make_wire 460 290 460 230 + make_wire 630 290 630 360 + make_wire 630 290 630 270 + make_wire 570 420 400 420 + make_wire 570 420 570 490 + make_wire 570 420 570 230 + make_wire 400 420 400 360 + make_wire 400 420 400 450 +} + diff --git a/technology/scn4m_subm/sue_lib/ms_flop.sue b/technology/scn4m_subm/sue_lib/ms_flop.sue new file mode 100644 index 00000000..85cc8e03 --- /dev/null +++ b/technology/scn4m_subm/sue_lib/ms_flop.sue @@ -0,0 +1,84 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_ms_flop {} { + make pmos -orient R90X -W 1.8u -L 0.6u -origin {40 250} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {40 380} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {-270 540} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {310 310} + make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {430 730} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {190 670} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {190 780} + make input -name clk -origin {-380 540} + make input -name din -origin {-370 320} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {720 250} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {720 380} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {990 310} + make pmos -orient R90X -W 1.8u -L 0.6u -origin {870 670} + make nmos -orient R270 -W 0.9u -L 0.6u -origin {870 780} + make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {620 540} + make output -name dout -origin {1410 310} + make output -name dout_bar -origin {1430 930} + make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {1110 730} + make_wire -330 160 40 160 + make_wire 40 160 40 190 + make_wire -370 320 0 320 + make_wire 360 310 480 310 + make_wire 460 730 480 730 + make_wire 230 730 380 730 + make_wire 100 310 100 720 + make_wire 100 720 150 720 + make_wire 100 310 80 310 + make_wire 100 310 280 310 + make_wire 0 250 0 320 + make_wire 0 320 0 380 + make_wire 80 250 80 310 + make_wire 80 310 80 380 + make_wire 40 440 40 540 + make_wire -330 840 190 840 + make_wire 230 670 230 730 + make_wire 230 730 230 780 + make_wire 150 670 150 720 + make_wire 150 720 150 780 + make_wire 190 540 190 610 + make_wire -330 540 -330 840 + make_wire -220 540 40 540 + make_wire 40 540 190 540 + make_wire -380 540 -330 540 + make_wire -330 540 -300 540 + make_wire -330 540 -330 160 + make_wire 720 160 720 190 + make_wire 1140 730 1160 730 + make_wire 780 310 780 720 + make_wire 780 720 830 720 + make_wire 780 310 760 310 + make_wire 780 310 960 310 + make_wire 680 320 680 380 + make_wire 760 250 760 310 + make_wire 760 310 760 380 + make_wire 720 440 720 540 + make_wire 910 670 910 730 + make_wire 910 730 910 780 + make_wire 830 670 830 720 + make_wire 830 720 830 780 + make_wire 870 540 870 610 + make_wire 720 540 870 540 + make_wire 670 540 720 540 + make_wire 480 310 480 730 + make_wire 1160 310 1160 730 + make_wire 530 540 530 160 + make_wire 530 160 720 160 + make_wire 530 540 190 540 + make_wire 530 540 590 540 + make_wire 530 540 530 840 + make_wire 530 840 870 840 + make_wire 680 310 480 310 + make_wire 680 310 680 250 + make_wire 680 310 680 320 + make_wire 950 730 910 730 + make_wire 950 730 1060 730 + make_wire 1040 310 1160 310 + make_wire 1160 310 1410 310 + make_wire 950 930 1430 930 + make_wire 950 730 950 930 +} + diff --git a/technology/scn4m_subm/sue_lib/replica_cell_6t.sue b/technology/scn4m_subm/sue_lib/replica_cell_6t.sue new file mode 100644 index 00000000..56e72056 --- /dev/null +++ b/technology/scn4m_subm/sue_lib/replica_cell_6t.sue @@ -0,0 +1,49 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_replica_cell_6t {} { + make inout -name BL -origin {190 360} + make inout -name BR -origin {830 360} + make input -name WL -origin {240 120} + make global -orient RXY -name vdd -origin {520 160} + make global -name gnd -origin {510 600} + make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} + make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} + make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} + make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} + make nmos -W 2.4u -L 0.6u -origin {630 490} + make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} + make_wire 630 550 630 530 + make_wire 400 530 400 550 + make_wire 400 190 400 170 + make_wire 630 170 630 190 + make_wire 400 360 400 270 + make_wire 630 360 630 450 + make_wire 630 360 700 360 + make_wire 270 300 270 120 + make_wire 270 120 740 120 + make_wire 740 120 740 300 + make_wire 230 360 190 360 + make_wire 780 360 830 360 + make_wire 510 550 400 550 + make_wire 510 550 630 550 + make_wire 510 550 510 600 + make_wire 520 170 400 170 + make_wire 520 170 630 170 + make_wire 520 160 520 170 + make_wire 240 120 270 120 + make_wire 460 290 630 290 + make_wire 460 290 460 490 + make_wire 460 290 460 230 + make_wire 630 290 630 360 + make_wire 630 290 630 270 + make_wire 570 420 400 420 + make_wire 570 420 570 490 + make_wire 570 420 570 230 + make_wire 400 420 400 360 + make_wire 400 420 400 450 + make_wire 320 360 320 550 + make_wire 320 550 400 550 + make_wire 320 360 310 360 + make_wire 320 360 400 360 +} + diff --git a/technology/scn4m_subm/sue_lib/sense_amp.sue b/technology/scn4m_subm/sue_lib/sense_amp.sue new file mode 100644 index 00000000..4d29e11a --- /dev/null +++ b/technology/scn4m_subm/sue_lib/sense_amp.sue @@ -0,0 +1,52 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_sense_amp {} { + make inout -name BL -origin {260 10} + make global -orient RXY -name vdd -origin {490 170} + make global -name gnd -origin {480 660} + make input -name sclk -origin {180 610} + make nmos -W 3.9u -L 0.6u -origin {600 500} + make nmos -orient RX -W 3.9u -L 0.6u -origin {370 500} + make pmos -orient RY -W 3u -L 0.6u -origin {600 240} + make pmos -orient RXY -W 3u -L 0.6u -origin {370 240} + make nmos -W 3.9u -L 0.6u -origin {480 610} + make inout -name BR -origin {710 20} + make pmos -W 3.9u -L 0.6u -origin {710 90} + make pmos -orient RX -W 3.9u -L 0.6u -origin {260 90} + make output -orient RXY -name dout -origin {110 370} + make_wire 600 560 600 540 + make_wire 370 540 370 560 + make_wire 370 200 370 180 + make_wire 600 180 600 200 + make_wire 490 180 370 180 + make_wire 490 180 600 180 + make_wire 490 170 490 180 + make_wire 430 300 600 300 + make_wire 430 300 430 500 + make_wire 430 300 430 240 + make_wire 600 300 600 280 + make_wire 540 430 370 430 + make_wire 540 430 540 500 + make_wire 540 430 540 240 + make_wire 370 430 370 460 + make_wire 480 560 600 560 + make_wire 480 560 370 560 + make_wire 480 560 480 570 + make_wire 480 650 480 660 + make_wire 420 610 180 610 + make_wire 650 90 320 90 + make_wire 600 360 710 360 + make_wire 710 360 710 130 + make_wire 600 360 600 300 + make_wire 600 360 600 460 + make_wire 370 370 260 370 + make_wire 260 370 260 130 + make_wire 370 370 370 430 + make_wire 370 370 370 280 + make_wire 260 10 260 50 + make_wire 710 20 710 50 + make_wire 320 90 180 90 + make_wire 180 90 180 610 + make_wire 110 370 260 370 +} + diff --git a/technology/scn4m_subm/sue_lib/tri_gate.sue b/technology/scn4m_subm/sue_lib/tri_gate.sue new file mode 100644 index 00000000..d296171f --- /dev/null +++ b/technology/scn4m_subm/sue_lib/tri_gate.sue @@ -0,0 +1,37 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_tri_gate {} { + make global -orient RXY -name vdd -origin {630 150} + make global -name gnd -origin {630 570} + make input -name tri_in -origin {320 340} + make output -name tri_out -origin {690 360} + make input -name en -origin {570 410} + make input -name en_bar -origin {570 310} + make nmos -W 1.2u -L 0.6u -origin {630 490} + make nmos -W 1.2u -L 0.6u -origin {630 410} + make pmos -orient RY -W 2.4u -L 0.6u -origin {630 310} + make pmos -orient RY -W 2.4u -L 0.6u -origin {630 230} + make pmos -orient RY -W 2.4u -L 0.6u -origin {380 290} + make nmos -W 1.2u -L 0.6u -origin {380 400} + make_wire 570 490 470 490 + make_wire 470 230 570 230 + make_wire 630 550 380 550 + make_wire 380 550 380 440 + make_wire 630 550 630 570 + make_wire 630 550 630 530 + make_wire 630 170 380 170 + make_wire 380 170 380 250 + make_wire 630 170 630 190 + make_wire 630 170 630 150 + make_wire 320 340 320 400 + make_wire 320 340 320 290 + make_wire 380 340 470 340 + make_wire 380 340 380 330 + make_wire 380 340 380 360 + make_wire 470 340 470 490 + make_wire 470 340 470 230 + make_wire 630 360 630 350 + make_wire 630 360 630 370 + make_wire 630 360 690 360 +} + diff --git a/technology/scn4m_subm/sue_lib/write_driver.sue b/technology/scn4m_subm/sue_lib/write_driver.sue new file mode 100644 index 00000000..de3909a7 --- /dev/null +++ b/technology/scn4m_subm/sue_lib/write_driver.sue @@ -0,0 +1,44 @@ +# SUE version MMI_SUE5.0.7 + +proc SCHEMATIC_write_driver {} { + make inout -name BL -origin {550 260} + make inout -name BR -origin {830 250} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {280 520} + make nand2 -WP 2.1u -WN 2.1u -origin {90 360} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {270 360} + make nmos -W 3.6u -L 0.6u -origin {830 410} + make nmos -W 3.6u -L 0.6u -origin {710 610} + make global -name gnd -origin {710 690} + make nand2 -WP 2.1u -WN 2.1u -origin {90 520} + make nmos -W 3.6u -L 0.6u -origin {550 410} + make input -name wen -origin {-290 340} + make input -name din -origin {-290 380} + make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {-80 540} + make_wire 160 360 240 360 + make_wire 830 250 830 370 + make_wire 550 260 550 370 + make_wire 550 450 550 560 + make_wire 550 560 710 560 + make_wire 710 560 710 570 + make_wire 710 560 830 560 + make_wire 830 560 830 450 + make_wire 710 650 710 690 + make_wire 250 520 160 520 + make_wire 770 410 770 520 + make_wire 770 520 330 520 + make_wire 320 360 490 360 + make_wire 490 360 490 410 + make_wire -180 380 -290 380 + make_wire -180 380 70 380 + make_wire -180 540 -110 540 + make_wire -180 380 -180 540 + make_wire -30 540 70 540 + make_wire 20 340 20 500 + make_wire 20 500 70 500 + make_wire 20 340 70 340 + make_wire -240 340 -240 610 + make_wire -240 610 650 610 + make_wire -240 340 20 340 + make_wire -240 340 -290 340 +} + diff --git a/technology/scn4m_subm/tech/LICENSE.txt b/technology/scn4m_subm/tech/LICENSE.txt new file mode 100644 index 00000000..0d923fcb --- /dev/null +++ b/technology/scn4m_subm/tech/LICENSE.txt @@ -0,0 +1,10 @@ +The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following +license information: +--------------------------------------------------------------- +Tim Edwards +Open Circuit Design +v1.0 April 2013 +v1.1 May 2015 +v1.2 April 2017 +--------------------------------------------------------------- +GPL Copyright (c) 2017 diff --git a/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech b/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech new file mode 100644 index 00000000..bb2c2490 --- /dev/null +++ b/technology/scn4m_subm/tech/SCN4M_SUBM.20.tech @@ -0,0 +1,7738 @@ +tech + format 29 + scmos +end + +version + version 2001a + description "SCMOS: Submit as technology.lambda: SCN4M_SUBM.20 [to process: TSMC35]" +end + +planes + well,w + implant,i + select,s + active,a + metal1,m1 + metal2,m2 + metal3,m3 + metal4,m4 + oxide,ox + comment + xp + contact + via1,v1 + via2,v2 + via3,v3 + fill +end + +types + well nwell,nw + active nwr + well pwell,pw + implant n_field_implant,nfi + implant p_field_implant,pfi + select nselect,ns + select pselect,ps + active ntransistor,nfet + active ptransistor,pfet + active diffusion,diff + active transistor,fet + active ndiffusion,ndif,green + active pdiffusion,pdif,brown + active ndcontact,ndc + active pdcontact,pdc + active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd + active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd + active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc + active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc + active nwsd + active nwsc + active polysilicon,red,poly,p + active polycontact,pcontact,polycut,pc + contact genericcontact,gcontact,gc + metal1 metal1,m1,blue + metal1 pseudo_rmetal1,prm1 + metal1 rmetal1,rm1 + metal1 fillm1,fm1 + metal1 m2contact,m2cut,m2c,via1,v1 + metal2 metal2,m2,purple + metal2 pseudo_rmetal2,prm2 + metal2 rmetal2,rm2 + metal2 fillm2,fm2 + via1 gv1 + metal2 m3contact,m3cut,m3c,via2,v2 + metal3 metal3,m3,cyan + metal3 pseudo_rmetal3,prm3 + metal3 rmetal3,rm3 + metal3 fillm3,fm3 + via2 gv2 + metal3 m4contact,m4cut,m4c,via3,v3 + metal4 metal4,m4,yellow + metal4 pseudo_rmetal4,prm4 + metal4 rmetal4,rm4 + metal4 fillm4,fm4 + via3 gv3 + metal4 pad + oxide glass + active silicide_block,sb + active poly_resist,pres + active pseudo_rpoly,prp + active rpoly,rp + active pseudo_rndiffusion,prnd + active rndiffusion,rndiff,rnd + active pseudo_rpdiffusion,prpd + active rpdiffusion,rpdiff,rpd + active pseudo_rnwell,prnwell,prnw + active rnwell,rnw + active pseudo_nwr,pnwr + implant filln,fn + fill filla,fa + fill fillb,fb + active fillp,fp + active fillapm,fapm + active activen_resist,anres + active activep_resist,apres + xp xp + xp m1p + xp m2p + xp m3p + xp m4p + comment comment + comment bb +end + +contact + pc poly metal1 + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + nwsc nwsd metal1 + psc psd metal1 + m2c metal1 metal2 + m3c metal2 metal3 + m4c metal3 metal4 + stackable pc m2c pm12contact,pm12c + stackable pdc m2c pdm12contact,pdm12c + stackable psc m2c psm12contact,psm12c,pom12c,pwm12c + stackable ndc m2c ndm12contact,ndm12c + stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c + stackable nwsc m2c nwsm12contact,nwsm12c + stackable m2c m3c m123contact,m123c + stackable m3c m4c m234contact,m234c +end + +styles + styletype mos + nwr 54 + pnwr 53 + nwsd 3 54 + nwsc 3 20 32 54 + nwell 12 + pwell 13 + nfi 53 + pfi 54 + nselect 43 + pselect 44 + diff 25 + tran 2 4 + ndiff 2 + pdiff 4 + nsd 3 + psd 5 + nfet 6 7 + pfet 8 9 + ndc 2 20 32 + pdc 4 20 32 + nsc 3 20 32 + psc 5 20 32 + poly 1 + pcontact 1 20 32 + gc 32 + metal1 20 + rm1 20 48 + prm1 48 + m1p 20 34 + fm1 20 34 + fp 1 34 + fa 32 + fb 45 34 + fn 45 34 + fapm 1 20 21 34 + gv1 55 + m2contact 20 21 55 + metal2 21 + rm2 21 48 + prm2 48 + m2p 21 34 + fm2 21 34 + gv2 56 + m3contact 21 22 56 + metal3 22 + rm3 22 48 + prm3 48 + m3p 22 34 + fm3 22 34 + gv3 57 + m4contact 22 23 57 + metal4 23 + rm4 23 48 + prm4 48 + m4p 23 34 + fm4 23 34 + pad 22 23 34 38 + glass 34 + xp 25 34 + sb 10 + pres 47 48 + rp 47 48 + prp 48 + anres 2 48 + rnd 2 48 + prnd 48 + apres 4 53 + rpd 4 53 + prpd 53 + rnw 12 53 + prnw 54 + comment 45 + bb 32 + error_p 42 + error_s 42 + error_ps 42 + magnet 54 + rotate 57 + fence 59 +end + +compose + compose nfet poly ndiff + compose pfet poly pdiff + paint diff nselect ndiff + paint diff pselect pdiff + compose tran poly diff + paint tran nselect nfet + paint tran pselect pfet + paint psd ns ndiff + paint nsd ps pdiff + paint ndiff ps psd + paint pdiff ns nsd + paint pad m1 pad + paint pad m2 pad + paint pad m2c pad + paint pfi nwell nfi + paint nfi pwell pfi + paint anres nwell apres + paint apres pwell anres + paint ndc nwell pdc + paint nfet nwell pfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint pdc pwell ndc + paint pfet pwell nfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint pad m3 pad + paint pad m4 pad + compose pres poly sb + paint sb poly pres + paint poly sb pres + erase pres sb poly + compose anres ndiff sb + paint sb ndiff anres + paint ndiff sb anres + erase anres sb ndiff + compose apres pdiff sb + paint sb pdiff apres + paint pdiff sb apres + erase apres sb pdiff +#CRE/CRM + compose rm1 prm1 m1 + compose rm2 prm2 m2 + compose rm3 prm3 m3 + compose rm4 prm4 m4 + compose rp prp poly + compose rnd prnd ndiff + compose rpd prpd pdiff + paint nwell rnw space + paint nwell nwr space + paint nwell prnw space + paint poly fp fp + paint m1 fm1 fm1 + paint m2 fm2 fm2 + paint m3 fm3 fm3 + paint m4 fm4 fm4 +end + +connect + nwell,nsc/a,nwsc/a,nsd,nwsd nwell,nsc/a,nwsc/a,nsd,nwsd + pwell,psc/a,psd pwell,psc/a,psd + m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 + m3,fm3,fapm,m3c/m3,m4c/m3,m4c/m3 m3,fm3,fapm,m3c/m3,m4c/m3,m4c/m3 + m4,fm4,fapm,m4c/m4 m4,fm4,fapm,m4c/m4 + ndiff,nsd,nwsd,ndc/a,nsc/a,nwsc/a,pdiff,psd,pdc/a,psc/a ndiff,nsd,nwsd,ndc/a,nsc/a,nwsc/a,pdiff,psd,pdc/a,psc/a + poly,fp,nfet,pfet,fet,fapm,pc/a poly,fp,nfet,pfet,fet,fapm,pc/a + gc poly,fp,ndiff,pdiff,nsd,nwsd,psd,m1,fm1,fapm,m2c/m1 + gv1 m1,fm1,fapm,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2,fm2,fapm,m3c/m2 + gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm,m4c/m3 + gv3 m3,fm3,fapm,m3c/m3,m4c/m3,m4,fm4,fapm + pad m1,fm1,m2,fm2,m3,fm3,m4,fm4 + rm1 prm1 + rm2 prm2 + rm3 prm3 + rm4 prm4 + rnw prnw + nwr pnwr + rp prp + rnd prnd + rpd prpd + pres sb + anres sb + apres sb +end + +cifoutput + +style lambda=0.20(p) + scalefactor 20 10 + options calma-permissive-labels + + # This is a custom section to add bounding boxes in OpenRAM + layer BB bb + labels bb + calma 63 0 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + layer CWP pwell + bloat-or ndiff,anres,rnd,ndc/a,nfet * 120 + bloat-or psd,psc/a * 60 + bloat-or pfi * 80 + grow 60 + shrink 60 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCA nwsc/m1 + squares 40 40 60 + calma 48 0 + + layer CCA ndc/m1,nsc/m1 + squares 20 40 60 + calma 48 0 + + layer CCA pdc/m1,psc/m1 + squares 20 40 60 + calma 48 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCP pc/m1 + squares 20 40 60 + calma 47 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +style fill-only + scalefactor 20 10 + + layer 100 fp + calma 100 0 + + layer 101 fm1 + calma 101 0 + + layer 102 fm2 + calma 102 0 + + layer 103 fm3 + calma 103 0 + + layer 104 fm4 + calma 104 0 + + layer 109 fa + or fb + calma 109 0 + + layer 119 fn + calma 119 0 + +style fapm-boxes + +# this output style creates fill boxes automatically (to meet minimum +# density requirements for poly and metal layers) 5 microns outside of +# drawn layout IF: 1. you have a flattened version of your chip +# 2. over which you paint the special fill layer 'fa', preferably with +# a size that is a multiple of 10 + n * (10 + 4), 3. set 'cif +# ostype fapm-boxes' and cif out to a file (this actually creates the +# fill boxes on cif/strm layer '110' using the magic 'squares' +# command), 4. cif in the resulting file (which creates boxes on magic +# layer 'fapm') and place this cell onto your chip (and verify absence +# of drc errors or shorts), then 5. cif out under your regular cif out +# style, where the 'fapm' layer creates fill boxes on poly and all +# metal layers. + + scalefactor 20 10 + + templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a + or fm1,m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 + or fm3,m3,rm3,m3c/m3,m4c/m3,m4c/m3 + or fm4,m4,rm4,m4c/m4 + or glass,pad + grow 500 + and fa + + layer 110 fa + squares 0 200 80 + and-not CRIT + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + +style fapm-stripes + scalefactor 20 10 + +# this output style creates the above layer 110 as stripes for reduced size +# HOWEVER it requires each 'fa' box to first be an exact multiple as above +# and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box +# to be a 1-lambda wide layer 'fb' box -- else you won't get strips! + + templayer CRIT fapm,fn,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,pres,rp,nfet,pfet,fet,pc/a + or fm1,m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2 + or fm3,m3,rm3,m3c/m3,m4c/m3,m4c/m3 + or fm4,m4,rm4,m4c/m4 + or glass,pad + grow 500 + and fa + + templayer FB fa + or fb + squares 0 200 80 + and-not CRIT + + layer 110 fa + squares 0 200 80 + and-not CRIT + or FB + shrink 90 + grow 90 + or fapm + labels fapm + calma 110 0 + + +style lambda=0.20(cp) + scalefactor 20 10 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + layer CWP pwell + bloat-or ndiff,anres,rnd,ndc/a,nfet * 120 + bloat-or psd,psc/a * 60 + bloat-or pfi * 80 + grow 60 + shrink 60 + and-not CWN + labels pwell + calma 41 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCC nwsc/m1 + squares 40 40 60 + calma 25 0 + + layer CCC ndc/m1,nsc/m1 + squares 20 40 60 + calma 25 0 + + layer CCC pdc/m1,psc/m1 + squares 20 40 60 + calma 25 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCC pc/m1 + squares 20 40 60 + calma 25 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.20(c) + scalefactor 20 10 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCC nwsc/m1 + squares 40 40 60 + calma 25 0 + + layer CCC ndc/m1,nsc/m1 + squares 20 40 60 + calma 25 0 + + layer CCC pdc/m1,psc/m1 + squares 20 40 60 + calma 25 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCC pc/m1 + squares 20 40 60 + calma 25 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + + +style lambda=0.20() + scalefactor 20 10 + + layer CWN nwell,rnw,nwr,nwsd,nwsc + bloat-or pdiff,apres,rpd,pdc/a,pfet * 120 + bloat-or nsd,nsc/a * 60 + bloat-or nfi * 80 + grow 60 + shrink 60 + labels nwell,rnw,nwr,nwsd,nwsc + calma 42 0 + + layer CWNR nwsd,nwsc,nwr + grow 140 + calma 91 0 + + layer CWND nwr + labels nwr + calma 92 0 + + layer CAA nwsd,nwsc,nwr + grow 100 + labels nwsd,nwsc + calma 43 0 + + layer CSN + bloat-or nwsd,nwsc * 80 nwr 0 + calma 43 0 + + templayer TNWR + bloat-or nwr * 100 nwsd,nwsc 40 + + templayer TCSB nwsd,nwsc + grow 40 + and-not TNWR + + layer CSB nwsd,nwsc,nwr + grow 140 + and-not TCSB + calma 29 0 + + layer CRNW pnwr + labels pnwr + calma 93 0 + + templayer TNS ns + + templayer TPS ps + +#we give priority to selects autogenerated around diffusions (vrs. ohmics) +#XDP = (pdiff*40) Or ps +#XDN = (ndiff*40) Or ns +#FSP = ((pdiff*40,psc*40) Or XDP And-Not XDN Or ps shrink-grow +#FSN = ((ndiff*40,nsc*40) Or XDN And-Not FDP Or ns shrink-grow +#CSN = FSN +#CSP = FSP + +#diffusion auto-nselect (will have priority) + templayer XDN + bloat-or ndiff,anres,rnd,ndc/a * 40 psd,psc/a 0 + or TNS + +#diffusion auto-pselect (will have priority) + templayer XDP + bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0 + or TPS + +#final pselect + templayer FSP + bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0 + or XDP +#give diff nselect priority + and-not XDN + or TPS + shrink 20 + grow 20 + grow 20 + shrink 20 + +#final nselect + templayer FSN + bloat-or ndiff,anres,rnd,nfet,nsd,nwsd,ndc/a,nsc/a,nwsc/a,nfet * 40 pdiff,apres,rpd,pdc/a,psd,psc/a,pfet 0 + and-not nwr + or XDN +#never conflict with final pselect + and-not FSP +#drawn select always goes + or TNS + shrink 20 + grow 20 + grow 20 + shrink 20 + + layer CSN FSN + calma 45 0 + + layer CSP FSP + calma 44 0 + + layer CAA diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + labels diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,pfet,pfet,fet + calma 43 0 + + layer CCA nwsc/m1 + squares 40 40 60 + calma 48 0 + + layer CCA ndc/m1,nsc/m1 + squares 20 40 60 + calma 48 0 + + layer CCA pdc/m1,psc/m1 + squares 20 40 60 + calma 48 0 + + layer CPG poly,pres,rp,nfet,pfet,fet,pc/a + labels poly,pres,rp,nfet,pfet,fet,pc/a + calma 46 0 + + layer CCP pc/m1 + squares 20 40 60 + calma 47 0 + + layer CCC gc + squares 0 40 60 + calma 25 0 + + layer CV1 m2c/m1 + squares 20 40 60 + calma 50 0 + + layer CV1 gv1 + squares 0 40 60 + calma 50 0 + + layer CV2 m3c/m2 + squares 20 40 60 + calma 61 0 + + layer CV2 gv2 + squares 0 40 60 + calma 61 0 + + layer CV3 m4c/m3 + squares 20 40 60 + calma 30 0 + + layer CV3 gv3 + squares 0 40 60 + calma 30 0 + + + templayer XPAD1 pad + shrink 120 + + templayer XPAD2 XPAD1 + shrink 120 + + layer CM4 pad + labels pad + calma 31 0 + + layer CV3 XPAD2 + squares 40 40 200 + calma 30 0 + + layer CM3 pad + labels pad + calma 62 0 + + layer CV2 XPAD2 + squares 160 40 200 + calma 61 0 + + layer CM2 pad + labels pad + calma 51 0 + + layer CV1 XPAD2 + squares 40 40 200 + calma 50 0 + + layer CM1 pad + calma 49 0 + + layer CM1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + labels m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 + calma 49 0 + + layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2 + labels m2,rm2,m2c/m2,m3c/m2,m3c/m2 + calma 51 0 + + layer CMFP m1p + labels m1p + calma 81 0 + + layer CMSP m2p + labels m2p + calma 82 0 + + layer 100 fp + labels fp + calma 100 0 + + layer 101 fm1 + labels fm1 + calma 101 0 + + layer 102 fm2 + labels fm2 + calma 102 0 + + layer 103 fm3 + labels fm3 + calma 103 0 + + layer 104 fm4 + labels fm4 + calma 104 0 + + layer 109 fa + or fb + squares 0 200 80 + labels fa + calma 109 0 + + layer 119 fn + calma 119 0 + + layer 110 fapm + labels fapm + calma 110 0 + +# layer CPG fp + layer CPG fp,fapm + squares 0 200 80 + labels fp + calma 46 0 + +# layer CM1 fm1 + layer CM1 fm1,fapm + squares 0 200 80 + labels fm1 + calma 49 0 + +# layer CM2 fm2 + layer CM2 fm2,fapm + + squares 0 200 80 + labels fm2 + calma 51 0 + +# layer CM3 fm3 + layer CM3 fm3,fapm + + squares 0 200 80 + labels fm3 + calma 62 0 + + layer CM3 m3,rm3,m3c/m3,m4c/m3,m4c/m3 + labels m3,rm3,m3c/m3,m4c/m3,m4c/m3 + calma 62 0 + + layer CMTP m3p + labels m3p + calma 83 0 + + layer CM4 m4,rm4,m4c/m4 + labels m4,rm4,m4c/m4 + calma 31 0 + + layer CMQP m4p + labels m4p + calma 84 0 + +# layer CM4 fm4 + layer CM4 fm4,fapm + + squares 0 200 80 + labels fm4 + calma 31 0 + + layer COG pad + shrink 500 + labels pad + calma 52 0 + + layer COG glass + labels glass + calma 52 0 + + layer CFI nfi,pfi + labels nfi,pfi + calma 27 0 + + layer CSB sb,pres,anres,apres + labels sb,pres,anres,apres + calma 29 0 + +#CRE/CRM + layer CRW rnw,prnw + labels rnw,prnw + calma 65 0 + layer CRG rp,prp,pres + labels rp,prp,pres + calma 67 0 + layer CRD rnd,rpd,prnd,prpd,anres,apres + labels rnd,rpd,prnd,prpd,anres,apres + calma 66 0 + layer CRE rnw,rp,rnd,rpd,pres,anres,apres + labels rnw,rp,rnd,rpd,pres,anres,apres + calma 64 0 + layer CRF rm1,prm1 + labels rm1,prm1 + calma 71 0 + layer CRS rm2,prm2 + labels rm2,prm2 + calma 72 0 + layer CRT rm3,prm3 + labels rm3,prm3 + calma 73 0 + layer CRQ rm4,prm4 + labels rm4,prm4 + calma 74 0 +#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3,rm4,prm4 +#CRE/CRM calma 70 0 + + layer CX comment + labels comment + calma 63 0 + + layer XP pad,xp + labels pad,xp + calma 26 0 + +end + +cifinput + +style lambda=0.20(p) + scalefactor 20 + + # This is a custom section to add bounding boxes in OpenRAM + layer bb BB + labels BB + calma 63 0 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer gv3 CV3 + and-not COP + and-not CM3 + calma CV3 30 * + + layer gv3 CV3 + and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + + + + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not XP + grow 20 + and CM3 + and CM2 + grow 10 + shrink 10 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + + layer m4 CM4 + and-not CRM + and-not CRQ + and-not XP + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer m4c CV3 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(s) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer gv3 CV3 + and-not COP + and-not CM3 + calma CV3 30 * + + layer gv3 CV3 + and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + + + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + + + + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not XP + grow 20 + and CM3 + and CM2 + grow 10 + shrink 10 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + + layer m4 CM4 + and-not CRM + and-not CRQ + and-not XP + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer m4c CV3 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(ps) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer gv3 CV3 + and-not COP + and-not CM3 + calma CV3 30 * + + layer gv3 CV3 + and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + + + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + + + + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20() + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer ndc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer ndc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nsc CAA + and CSN + and CCA + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer nsc CAA + and CSN + and CCC + and-not CWNR + and-not CTA + + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer nwsc CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CCA + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCA 48 * + + layer nwsc CAA + and CSN + and CWNR + shrink 105 + and-not CTA + and CCC + + and CWN + and CM1 + grow 40 + grow 10 + shrink 10 + calma CCC 25 * + + layer pdc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer pdc CAA + and CSP + and CCC + and-not CTA + + and-not CPS + and CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer psc CAA + and CSP + and CCA + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCA 48 * + + layer psc CAA + and CSP + and CCC + and-not CWNR + and-not CTA + + and-not CPS + and-not CWN + and CM1 + grow 20 + grow 10 + shrink 10 + calma CCC 25 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer pc CCP + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCP 47 * + + layer pc CCC + and CPG + and-not CPC + and-not CEL + and-not CAA + grow 20 + and CM1 + grow 10 + shrink 10 + calma CCC 25 * + + layer gc CCP + and-not CPG + and-not CPC + calma CCP 47 * + + layer gc CCP + and-not CM1 + calma CCP 47 * + + layer gc CCA + and-not COP + and-not CAA + and-not CBA + calma CCA 48 * + + layer gc CCA + and-not COP + and-not CM1 + calma CCA 48 * + + layer gc CCC + and-not COP + and-not CPG + and-not CPC + and-not CEL + and-not CAA + and-not CBA + calma CCC 25 * + + layer gc CCC + and-not COP + and-not CM1 + calma CCC 25 * + + layer gc CCE + and-not CPC + and-not CEL + calma CCE 55 * + + layer gc CCE + and-not CM1 + calma CCE 55 * + + layer gv1 CV1 + and-not COP + and-not CM1 + calma CV1 50 * + + layer gv1 CV1 + and-not COP + and-not CM2 + calma CV1 50 * + + layer gv2 CV2 + and-not COP + and-not CM2 + calma CV2 61 * + + layer gv2 CV2 + and-not COP + and-not CM3 + calma CV2 61 * + + layer gv3 CV3 + and-not COP + and-not CM3 + calma CV3 30 * + + layer gv3 CV3 + and-not COP + and-not CM4 + calma CV3 30 * + + layer m2c CV1 + and-not XP + grow 20 + and CM2 + and CM1 + grow 10 + shrink 10 + calma CV1 50 * + + + + + layer m1 CM1 + and-not CRM + and-not CRF + and-not XP + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer m2 CM2 + and-not CRM + and-not CRS + and-not XP + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + + + + + + + + + + + + + + + + + + + + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer m3c CV2 + and-not XP + grow 20 + and CM3 + and CM2 + grow 10 + shrink 10 + calma CV2 61 * + + + layer m3 CM3 + and-not CRM + and-not CRT + and-not XP + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + + layer m4 CM4 + and-not CRM + and-not CRQ + and-not XP + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer m4c CV3 + and-not XP + grow 20 + and CM4 + and CM3 + grow 20 + shrink 20 + calma CV3 30 * + + layer pad XP + labels pad + calma XP 26 * + + layer glass COG + and-not COP + and-not XP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(c) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(cs) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + + ignore CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(cps) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer nselect CSN + calma CSN 45 * + + layer pselect CSP + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + + +style lambda=0.20(cp) + scalefactor 20 + + layer nwell CWN + and-not CWNR + and-not CTA + labels CWN + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRE + and-not CSB + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer rnw CWN + and-not CWNR + and CRW + and-not CRD + and-not CAA + and-not CPG + calma CWN 42 * + + layer pseudo_rnwell CRW + and-not CRE + calma CRW 65 * + + calma CWNR 91 * + + layer nwr CWND + calma CWND 92 * + + layer pseudo_nwr CRNW + calma CRNW 93 * + + layer pwell CWP + and-not CTA + labels CWP + calma CWP 41 * + + layer diff CAA + and-not CTA + and-not CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + layer tran CAA + and-not CTA + and CPG + and-not CWNR + and-not COP + and-not CSN + and-not CSP + labels CAA + calma CAA 43 * + + calma CSN 45 * + + calma CSP 44 * + + layer ndiff CAA + and CSN + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRE + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer rnd CAA + and CSN + and-not CWNR + and CRD + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rndiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and-not CWN + and-not CSP + and CSN + and-not CBA + calma CRD 66 * + + layer pdiff CAA + and CSP + and-not CWNR + and-not CTA + and-not CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRE + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer rpd CAA + and CSP + and-not CWNR + and CRD + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CAA 43 * + + layer pseudo_rpdiff CRD + and-not CRE + and-not CAA + and-not CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + calma CRD 66 * + + layer nfet CAA + and CSN + and-not CWNR + and-not CTA + and CPG + and-not CEL + and-not CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer pfet CAA + and CSP + and-not CWNR + and-not CTA + and CPG + and-not CEL + and CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nsd CAA + and CSN + and-not CWNR + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer psd CAA + and CSP + and-not CWNR + and-not CTA + and-not CWN + and-not CSN + and-not CPS + and CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer nwsd CAA + and CSN + and CWNR + shrink 100 + and-not CTA + and CWN + and-not CSP + and-not CBA + labels CAA + calma CAA 43 * + + layer gc CCA + and CPG + and-not CEL + calma CCA 48 * + + layer gc CCP + and CPG + and-not CEL + calma CCP 47 * + + layer gc CCC + and CPG + and-not CEL + calma CCC 25 * + + layer gc CCE + and CPG + and-not CEL + calma CCE 55 * + + layer gc CCA + and-not COP + and-not CPC + and-not CEL + calma CCA 48 * + + layer gc CCP + and-not COP + and-not CPC + and-not CEL + calma CCP 47 * + + layer gc CCC + and-not COP + and-not CPC + and-not CEL + calma CCC 25 * + + layer gc CCE + and-not COP + and-not CPC + and-not CEL + calma CCE 55 * + + layer poly CPG + and-not CRE + labels CPG + calma CPG 46 * + + layer rp CPG + and CRE + and-not CSB + calma CPG 46 * + + layer rp CPG + and CRG + calma CPG 46 * + + layer pseudo_rpoly CRG + and-not CRE + calma CRG 67 * + + layer m1 CM1 + and-not CRM + and-not CRF + labels CM1 + calma CM1 49 * + + layer rm1 CRM + and CM1 + calma CRM 70 * + + layer rm1 CRF + and CM1 + calma CRF 71 * + + layer pseudo_rmetal1 CRF + and-not rm1 + calma CRF 71 * + + layer m1p CMFP + labels CMFP + calma CMFP 81 * + + layer gv1 CV1 + calma CV1 50 * + + layer m2 CM2 + and-not CRM + and-not CRS + labels CM2 + calma CM2 51 * + + layer rm2 CRM + and CM2 + calma CRM 70 * + + layer rm2 CRS + and CM2 + calma CRS 72 * + + layer pseudo_rmetal2 CRS + and-not rm2 + calma CRS 72 * + + layer m2p CMSP + labels CMSP + calma CMSP 82 * + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + + layer gv2 CV2 + calma CV2 61 * + + layer m3 CM3 + and-not CRM + and-not CRT + labels CM3 + calma CM3 62 * + + layer rm3 CRM + and CM3 + calma CRM 70 * + + layer rm3 CRT + and CM3 + calma CRT 73 * + + layer pseudo_rmetal3 CRT + and-not rm3 + calma CRT 73 * + + layer m3p CMTP + labels CMTP + calma CMTP 83 * + + layer gv3 CV3 + calma CV3 30 * + + layer m4 CM4 + and-not CRM + and-not CRQ + labels CM4 + calma CM4 31 * + + layer rm4 CRM + and CM4 + calma CRM 70 * + + layer rm4 CRQ + and CM4 + calma CRQ 74 * + + layer pseudo_rmetal4 CRQ + and-not rm4 + calma CRQ 74 * + + layer m4p CMQP + labels CMQP + calma CMQP 84 * + + layer xp XP + calma XP 26 * + + layer glass COG + and-not COP + labels COG + calma COG 52 * + + layer nfi CFI + and CWN + labels CFI + calma CFI 27 * + + layer pfi CFI + and-not CWN + labels CFI + calma CFI 27 * + + layer sb CSB + and-not CWNR + labels CSB + calma CSB 29 * + + layer pres CPG + and CSB + calma CPG 46 * + + layer anres CAA + and CSN + and-not CWNR + and-not CTA + and CSB + and-not CPG + and-not CWN + and-not CSP + and-not CBA + calma CAA 43 * + + layer apres CAA + and CSP + and-not CWNR + and-not CTA + and CSB + and-not CPG + and CWN + and-not CSN + and-not CPS + and-not CBA + calma CAA 43 * + + layer comment CX + labels CX + calma CX 63 * + + calma CTA 60 * + + calma CRW 65 * + calma CRG 67 * + calma CRD 66 * + calma CRE 64 * + calma CRF 71 * + calma CRS 72 * + calma CRT 73 * + calma CRQ 74 * + calma CRM 70 * + +style fill-only + scalefactor 20 +# scalefactor 100 + + layer fp 100 + calma 100 100 * + + layer fm1 101 + calma 101 101 * + + layer fm2 102 + calma 102 102 * + + layer fm3 103 + calma 103 103 * + + layer fm4 104 + calma 104 104 * + + layer fa 109 + or fb + calma 109 109 * + + layer fn 119 + calma 119 119 * + + layer fapm 110 + calma 110 110 * + +end + +mzrouter + style irouter +# layer hCost vCost jogCost hintCost + layer metal4 2 1 2 1 + layer metal3 1 2 2 1 + layer metal2 2 1 2 1 + layer metal1 2 3 2 1 + layer poly 10 10 11 1 + contact m4contact metal4 metal3 4 + contact m3contact metal3 metal2 5 + contact m2contact metal2 metal1 6 + contact pcontact metal1 poly 7 + notactive poly pcontact + +style garouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + contact m2contact metal1 metal2 1024 + +end + +drc + width nwell 12 \ + "N-well width < 12 (Mosis #1.1)" + + width rnw 12 \ + "rnwell (for resistor L/W extraction) width < 12 (Mosis #1.1)" + + width nwr 12 \ + "nwr (for Fig1b resistor L/W extraction) width < 12 (Mosis #Fig1bX)" + + width pwell 12 \ + "P-well width < 12 (Mosis #1.1)" + + width diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 \ + "Diffusion width < 3 (Mosis #2.1)" + + edge4way nsd,nwsd,nsc/a,nwsc/a pdiff,apres,rpd,pdc/a 3 ~(nsd,nwsd,nsc/a,nwsc/a)/active pdiff,apres,rpd,pdc/a 3 \ + "P-Diffusion width in N-Ohmic < 3 (Mosis #2.1)" active + + edge4way psd,psc/a ndiff,anres,rnd,ndc/a 3 ~(psd,psc/a)/active ndiff,anres,rnd,ndc/a 3 \ + "N-Diffusion width in P-Ohmic < 3 (Mosis #2.1)" active + + edge4way pdiff,apres,rpd,pdc/a nsd,nwsd,nsc/a,nwsc/a 3 ~(pdiff,apres,rpd,pdc/a)/active nsd,nwsd,nsc/a,nwsc/a 3 \ + "N-Ohmic width in P-Diffusion < 3 (Mosis #2.1)" active + + edge4way ndiff,anres,rnd,ndc/a psd,psc/a 3 ~(ndiff,anres,rnd,ndc/a)/active psd,psc/a 3 \ + "P-Ohmic width in N-Diffusion < 3 (Mosis #2.1)" active + + width poly,fp,pres,rp,pc/a,nfet,pfet,fet 2 \ + "Poly width < 2 (Mosis #3.1)" + + width nselect 3 \ + "N-Select width < 3 (Mosis #4.4)" + + width pselect 3 \ + "P-Select width < 3 (Mosis #4.4)" + + width ndiff,anres,rnd,ndc/a,nsd,nsc/a 3 \ + "N-Diffusion,N-Ohmic width < 3 (Mosis #4.4)" + + width pdiff,apres,rpd,pdc/a,psd,psc/a 3 \ + "P-Diffusion,P-Ohmic width < 3 (Mosis #4.4)" + + width pc/m1 4 \ + "Poly contact width < 4 (Mosis #5.1)" + + + width gc 2 \ + "GC contact width < 2 (Mosis #6.1)" + + width ndc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width nsc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + width nwsc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + + width nwsc 6 \ + "nwr (for Fig1b resistor) active Contact width < 6 (Mosis #Fig1b)" + + width pdc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width psc/m1 4 \ + "Diffusion contact width < 4 (Mosis #6.1)" + + + width m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 \ + "Metal1 width < 3 (Mosis #7.1)" + + width gv1 2 \ + "GV1 via width < 2 (Mosis #8.1)" + + width m2c/m1 4 \ + "Metal2 contact width < 4 (Mosis #8.1)" + + + + + + + + + width m2,fm2,rm2,m2c/m2,m3c/m2 3 \ + "Metal2 width < 3 (Mosis #9.1)" + + width gv2 2 \ + "GV2 via width < 2 (Mosis #14.1)" + + width m3c/m2 4 \ + "Metal3 contact width < 4 (Mosis #14.1)" + + + + width m3,fm3,rm3,m3c/m3,m4c/m3 3 \ + "Metal3 width < 3 (Mosis #15.1)" + + width sb,pres,anres,apres 4 \ + "Silicide-Block width < 4 (Mosis #20.1)" + + width pres 5 \ + "Silicide-Block polyR width < 5 (Mosis #20.6)" + + width anres,apres 6 \ + "Silicide-Block activeR width < 6 (Mosis #20.16)" + + width gv3 2 \ + "GV3 via width < 2 (Mosis #21.3)" + + width m4c/m3 4 \ + "Metal4 contact width < 4 (Mosis #21.3)" + + + width m4,fm4,rm4,m4c/m4,pad 3 \ + "Metal4 width < 3 (Mosis #22.1)" + + width nfi,pfi 4 \ + "N/P_field-implant width < 4 (Mosis #29.1)" + + spacing nwell nwell 6 touching_ok \ + "N-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing pwell pwell 6 touching_ok \ + "P-well(at-same-potential) spacing < 6 (Mosis #1.3)" + + spacing rnw nwell 18 touching_illegal \ + "rnw (for resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" + + spacing nwr nwell 18 touching_illegal \ + "nwr (for Fig1b resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" + + edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ + "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active + + edge4way ~(pwell)/well pwell 1 ~(nwr)/active 0 0 \ + "P-well cannot touch nwr (for Fig1b resistor L/W extraction) (Mosis #1.4)" active + + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 touching_ok \ + "Diffusion spacing < 3 (Mosis #2.2)" + + spacing nwell ndiff,anres,rnd,nfet,ndc/a 6 touching_illegal \ + "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" + + spacing pwell pdiff,apres,rpd,pfet,pdc/a 6 touching_illegal \ + "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" + + spacing ndiff,anres,rnd,nfet,ndc/a pdiff,apres,rpd,pfet,pdc/a 12 touching_illegal \ + "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" + + edge4way ~(nwell)/well nwell 6 ~(pdiff,apres,rpd,pfet,pdc/a)/active nwell 6 \ + "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 6 ~(ndiff,anres,rnd,nfet,ndc/a)/active pwell 6 \ + "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active + + edge4way ~(nwell)/well nwell 3 ~(nsd,nwsd,nsc/a,nwsc/a)/active nwell 3 \ + "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active + + edge4way ~(pwell)/well pwell 3 ~(psd,psc/a)/active pwell 3 \ + "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active + + spacing ndiff,anres,rnd,ndc/a nsd,nwsd,nsc/a,nwsc/a 9 touching_illegal \ + "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing pdiff,apres,rpd,pdc/a psd,psc/a 9 touching_illegal \ + "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" + + spacing nwell psd,psc/a 3 touching_illegal \ + "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" + + spacing pwell nsd,nwsd,nsc/a,nwsc/a 3 touching_illegal \ + "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" + + spacing psd,psc/a rnw,prnw 3 touching_illegal \ + "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" + + spacing psd,psc/a nwr,pnwr 3 touching_illegal \ + "P-Ohmic spacing to nwr,pnwr (for Fig1b Resistor) < 3 (Mosis #2.4)" + + spacing nsd,nwsd,nsc/a,nwsc/a psd,psc/a 6 touching_illegal \ + "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" + + spacing ndiff,anres,rnd,nfet,ndc/a,nfet psd,psc/a 4 touching_ok \ + "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" + + spacing pdiff,apres,rpd,pfet,pdc/a,pfet nsd,nwsd,nsc/a,nwsc/a 4 touching_ok \ + "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" + + spacing poly,pres,rp,pc/a,nfet,pfet,fet poly,pres,rp,pc/a,nfet,pfet,fet 3 touching_ok \ + "Poly spacing < 3 (Mosis #3.2)" + + spacing poly,pres,rp,pc/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ + "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" + + spacing fp fp 4 touching_ok \ + "Poly fill layer (fp) spacing < 4 (Mosis #0)" + + edge4way nfet,pfet,fet space/active,poly,fp,pres,rp,pc/a 2 poly,fp,pres,rp,pc/a 0 0 \ + "Poly overhang of Transistor < 2 (Mosis #3.3)" active + + edge4way nfet,pfet,fet space/active,ndiff,anres,rnd,ndc/a,pdiff,apres,rpd,pdc/a 3 ndiff,anres,rnd,ndc/a,pdiff,apres,rpd,pdc/a,nfet,pfet,fet 0 0 \ + "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active + + edge4way poly,fp,rp,pc/a ~(poly,fp,pres,rp,pc/a,nfet,pfet,fet,prp)/active 1 space space 1 \ + "Poly spacing to Diffusion < 1 (Mosis #3.5)" + + edge4way nfet ~(nfet)/active 2 ~(pselect)/select ~(nfet)/active 2 \ + "N-Transistor space to P-Select < 2 (Mosis #4.1)" select + + edge4way pfet ~(pfet)/active 2 ~(nselect)/select ~(pfet)/active 2 \ + "P-Transistor space to N-Select < 2 (Mosis #4.1)" select + + edge4way nfet ~(nfet)/active 3 ~(psd,psc/a)/active ~(nfet)/active 2 \ + "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active + + edge4way pfet ~(pfet)/active 3 ~(nsd,nwsd,nsc/a,nwsc/a)/active ~(pfet)/active 2 \ + "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active + +#PEZ edge4way psd,psc/a space ~(nfet)/active space \ +#PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active + +#PEZ edge4way nsd,nwsd,nsc/a,nwsc/a space ~(pfet)/active space \ +#PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active + + edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active nselect,pselect 2 \ + "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active + + edge4way space nselect,pselect 2 ~(ndiff,anres,rnd,nfet,ndc/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active + + edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a)/active nselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active + + edge4way nselect,pselect space 2 ~(ndiff,anres,rnd,nfet,ndc/a)/active space,nselect,pselect 2 \ + "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active + + edge4way space nselect,pselect 2 ~(pdiff,apres,rpd,pfet,pdc/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active + + edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a)/active pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active + + edge4way nselect,pselect space 2 ~(pdiff,apres,rpd,pfet,pdc/a)/active space,nselect,pselect 2 \ + "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active + + area nsd,nwsd,psd,nsc/a,nwsc/a,psc/a 16 3 \ + "Ohmic-Diffusion area < 16 (Mosis #+++)" + + edge4way diff space 2 nselect space 2 \ + "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way diff space 2 pselect space 2 \ + "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select + + edge4way ndiff,anres,rnd,nfet,ndc/a space 2 ~(pselect)/select space 2 \ + "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select + + edge4way pdiff,apres,rpd,pfet,pdc/a space 2 ~(nselect)/select space 2 \ + "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select + + edge4way ~(pdiff,apres,rpd,pfet,pdc/a,psd,psc/a)/active pdiff,apres,rpd,pfet,pdc/a,psd,psc/a 1 ~(nselect)/select 0 0 \ + "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select + + edge4way ~(ndiff,anres,rnd,nfet,ndc/a,nsd,nwsd,nsc/a,nwsc/a)/active ndiff,anres,rnd,nfet,ndc/a,nsd,nwsd,nsc/a,nwsc/a 1 ~(pselect)/select 0 0 \ + "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select + + spacing nselect nselect 3 touching_ok \ + "N-Select spacing < 3 (Mosis #4.4)" + + spacing pselect pselect 3 touching_ok \ + "P-Select spacing < 3 (Mosis #4.4)" + + edge4way ndiff,anres,rnd,ndc/a psd,psc/a 2 ~(ndiff,anres,rnd,ndc/a)/active 0 0 \ + "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" + + edge4way pdiff,apres,rpd,pdc/a nsd,nwsd,nsc/a,nwsc/a 2 ~(pdiff,apres,rpd,pdc/a)/active 0 0 \ + "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" + + edge4way gc ~(gc)/contact 1 poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a ~(gc)/contact 1 \ + "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active + + edge4way ~(nwsd)/active nwsd 2 ~(gc)/contact nwsd 2 \ + "nwr (for Fig1b resistor) active overlap of GC contact < 2 (Mosis #Fig1b)" contact + + spacing nwr gc 5 touching_illegal \ + "nwr (for Fig1b resistor) spacing to GC contact < 5 (Mosis #Fig1b)" + + spacing nwr ndc/a,nsc/a,nwsc/a 3 touching_illegal \ + "nwr (for Fig1b resistor) spacing to Diffusion contact < 3 (Mosis #Fig1b)" + + edge4way gc space 1 poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a space 1 \ + "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active + + edge4way ~(poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active poly,fp,pres,rp,pc/a,diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 1 ~(gc)/contact 0 0 \ + "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact + + spacing gc gc 3 touching_ok \ + "Generic contact spacing < 3 (Mosis #5.3)" + + edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ + "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 + + spacing gv1 m2c/m2 2 touching_illegal \ + "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" + +#PSC spacing poly,fp,pres,rp,pc/a pc/a 4 touching_ok \ +#PSC "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" + + edge4way gc ~(gc)/contact 1 diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,poly,fp,pres,rp,pc/a ~(gc)/contact 1 \ + "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active + + spacing gc pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 2 touching_illegal \ + "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" + + spacing nsc/m1,nwsc/m1 pdc/m1 1 touching_illegal \ + "nsc spacing to pdc < 1 (Mosis #6.3)" + + spacing psc/m1 ndc/m1 1 touching_illegal \ + "psc spacing to ndc < 1 (Mosis #6.3)" + + + + + + + + + spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 1 touching_illegal \ + "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" + + spacing nfet,pfet gc 2 touching_illegal \ + "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" + + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a pc/a 1 touching_illegal \ + "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" + + spacing diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a,nfet,pfet ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 4 touching_ok \ + "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" + + spacing pc/a ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 2 touching_illegal \ + "pc/a,pm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a,nwsc/a < 2 (Mosis #6.7)" + + spacing m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 touching_ok \ + "Metal1 spacing < 3 (Mosis #7.2)" + + spacing m1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 fm1,fapm 3 touching_illegal \ + "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" + + spacing fm1 fm1 4 touching_ok \ + "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" + + edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ + "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact + + spacing gv1 gv1 3 touching_ok \ + "GV1 via spacing < 3 (Mosis #8.2)" + + edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 ~(gv1)/via1 1 \ + "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 + + edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ + "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 + + edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ + "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 + + spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 3 touching_ok \ + "Metal2 spacing < 3 (Mosis #9.2)" + + spacing m2,rm2,m2c/m2,m3c/m2 fm2,fapm 3 touching_illegal \ + "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" + + spacing fm2 fm2 4 touching_ok \ + "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" + + edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ + "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv1)/via1 0 0 \ + "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 + + width glass 10 \ + "COG width < 10 (Mosis #10.2)" + + edge4way ~(pad)/metal4 pad 30 ~(glass)/oxide pad 30 \ + "pad overlap of COG < 30 (Mosis #10.3)" oxide + + spacing gv2 gv2 3 touching_ok \ + "GV2 via spacing < 3 (Mosis #14.2)" + + spacing gv2 m3c/m2 2 touching_illegal \ + "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" + + edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ + "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 + + edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ + "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 + + spacing m3,rm3,m3c/m3,m4c/m3 m3,rm3,m3c/m3,m4c/m3 3 touching_ok \ + "Metal3 spacing < 3 (Mosis #15.2)" + + spacing m3,rm3,m3c/m3,m4c/m3 fm3,fapm 3 touching_illegal \ + "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" + + spacing fm3 fm3 4 touching_ok \ + "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" + + edge4way gv2 space 1 m3,fm3,rm3,m3c/m3,m4c/m3 space 1 \ + "Metal3 must overlap GV2 via by 1 (Mosis #15.3)" metal3 + + edge4way ~(m3,fm3,rm3,m3c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m4c/m3 1 ~(gv2)/via2 0 0 \ + "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 + + spacing sb,pres,anres,apres sb,pres,anres,apres 4 touching_ok \ + "Silicide-Block spacing < 4 (Mosis #20.2)" + + spacing sb,pres,anres,apres,pres,anres,apres pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a 1 touching_illegal \ + "Silicide-Block spacing to Diffusion contact,Poly contact < 1 (Mosis #20.3)" + + spacing sb,pres,anres,apres,pres,anres,apres gc 2 touching_illegal \ + "Silicide-Block spacing to GC contact < 2 (Mosis #20.3)" + + edge4way sb,pres,anres,apres space 2 ~(diff,ndiff,anres,rnd,nfet,nsd,nwsd,pdiff,apres,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a)/active 0 2 \ + "Silicide-Block space to Diffusion < 2 (Mosis #20.4)" active + + spacing sb,pres,anres,apres,pres poly,fp,pres,rp,pc/a 2 touching_ok \ + "Silicide-Block spacing to other Poly < 2 (Mosis #20.5)" + + edge4way sb,pres,anres,apres space 2 ~(poly,fp,pres,rp,pc/a)/contact sb,pres,anres,apres 2 \ + "Silicide-Block space to Poly < 2 (Mosis #20.5x)" contact + + spacing sb,pres,anres,apres,pres nfet,pfet,fet 2 touching_ok \ + "Silicide-Block spacing to other Transistor < 2 (Mosis #20.5)" + + edge4way sb,pres,anres,apres space 2 ~(nfet,pfet,fet)/contact sb,pres,anres,apres 2 \ + "Silicide-Block space to Transistor < 2 (Mosis #20.5x)" contact + + spacing pres pres 7 touching_ok \ + "Silicide-Block polyR spacing < 7 (Mosis #20.13)" + + edge4way pres,anres,apres space/active,sb 2 sb sb 2 \ + "Silicide-Block overlap of Silicide-Block polyR/activeR < 2 (Mosis #20.15)" + + edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 0 0 \ + "Diffusion overhang of Silicide-Block < 3 (Mosis #20.17) + + spacing gv3 gv3 3 touching_ok \ + "GV3 via spacing < 3 (Mosis #21.2)" + + spacing gv3 m4c/m3 2 touching_illegal \ + "GV3 via spacing to Metal4 contact < 2 (Mosis #21.2)" + + edge4way gv3 space 1 m3,fm3,rm3,m3c/m3,m4c/m3 space 1 \ + "Metal3 must overlap GV3 via by 1 (Mosis #21.3)" metal3 + + edge4way ~(m3,fm3,rm3,m3c/m3,m4c/m3)/metal3 m3,fm3,rm3,m3c/m3,m4c/m3 1 ~(gv3)/via3 0 0 \ + "Metal3(edge) cannot touch GV3 via (Mosis #21.3)" via3 + + spacing m4,rm4,m4c/m4,pad m4,rm4,m4c/m4,pad 3 touching_ok \ + "Metal4 spacing < 3 (Mosis #22.2)" + + spacing m4,rm4,m4c/m4,pad fm4,fapm 3 touching_illegal \ + "Metal4 spacing to fill layer (fm4) < 3 (Mosis #22.2)" + + spacing fm4 fm4 4 touching_ok \ + "Metal4 fill layer (fm4) spacing < 4 (Mosis #0)" + + edge4way gv3 space 1 m4,fm4,rm4,m4c/m4,pad space 1 \ + "Metal4 must overlap GV3 via by 1 (Mosis #22.3)" metal4 + + edge4way ~(m4,fm4,rm4,m4c/m4,pad)/metal4 m4,fm4,rm4,m4c/m4,pad 1 ~(gv3)/via3 0 0 \ + "Metal4(edge) cannot touch GV3 via (Mosis #22.3)" via3 + + spacing nfi nfi 4 touching_ok \ + "N_field-implant spacing < 4 (Mosis #35.2)" + + spacing pfi pfi 4 touching_ok \ + "P_field-implant spacing < 4 (Mosis #35.2)" + + spacing nfi pfi 4 touching_illegal \ + "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" + + spacing nwell,pdiff,apres,rpd,pfet,pdc/a pfi 4 touching_illegal \ + "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" + + spacing pwell,ndiff,anres,rnd,nfet,ndc/a nfi 4 touching_illegal \ + "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" + + edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ + "N-well overlap of N_field-implant < 4 (Mosis #21.2)" implant + + edge4way ~(pwell)/well pwell 4 ~(pfi)/implant pwell 4 \ + "P-well overlap of P_field-implant < 4 (Mosis #21.2)" implant + + spacing fa fapm 4 touching_illegal \ + "fill layer fa spacing to fill layer fapm < 4 (Mosis #0)" + + width fa 10 \ + "filla width < 10 (Mosis #0)" + + width fapm 10 \ + "fillapm width < 10 (Mosis #0)" + + width fp 10 \ + "fillp width < 10 (Mosis #0)" + + width fm1 10 \ + "fillm1 width < 10 (Mosis #0)" + + width fm2 10 \ + "fillm2 width < 10 (Mosis #0)" + + width fm3 10 \ + "fillm3 width < 10 (Mosis #0)" + + width fm4 10 \ + "fillm4 width < 10 (Mosis #0)" + + edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ + "Contact not rectangular (Magic rule)" + + edge4way fm4 ~(fm4)/metal4 1 ~(fm4)/metal4 (~(fm4),fm4)/metal4 1 \ + "Contact not rectangular (Magic rule)" + + edge4way rp space/active 1 prp 0 0 \ + "prp overhang of rpoly (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rnw space/active 1 prnw 0 0 \ + "prnw overhang of rnwell (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way nwr space/active 1 pnwr 0 0 \ + "pnwr overhang of nwr (for Fig1b resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rpd space/active 1 prpd 0 0 \ + "prpd overhang of rpdiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rnd space/active 1 prnd 0 0 \ + "prnd overhang of rndiff (for resistor L/W extraction) < 1 (Mosis #0)" active + + edge4way rm1 space/metal1 1 prm1 0 0 \ + "prm1 overhang of rmetal1 (for resistor L/W extraction) < 1 (Mosis #0)" metal1 + + edge4way rm2 space/metal2 1 prm2 0 0 \ + "prm2 overhang of rmetal2 (for resistor L/W extraction) < 1 (Mosis #0)" metal2 + + edge4way rm3 space/metal3 1 prm3 0 0 \ + "prm3 overhang of rmetal3 (for resistor L/W extraction) < 1 (Mosis #0)" metal3 + + edge4way rm4 space/metal4 1 prm4 0 0 \ + "prm4 overhang of rmetal4 (for resistor L/W extraction) < 1 (Mosis #0)" metal4 + + edge4way ndc/a,nsc/a,nwsc/a ~(ndc/a,nsc/a,nwsc/a)/active 1 ~(ndc/a,nsc/a,nwsc/a)/active (~(ndc/a,nsc/a,nwsc/a),ndc/a,nsc/a,nwsc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pdc/a,psc/a ~(pdc/a,psc/a)/active 1 ~(pdc/a,psc/a)/active (~(pdc/a,psc/a),pdc/a,psc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way pc/a ~(pc/a)/active 1 ~(pc/a)/active (~(pc/a),pc/a)/active 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m2c/m1 ~(m2c/m1)/metal1 1 ~(m2c/m1)/metal1 (~(m2c/m1),m2c/m1)/metal1 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m3c/m2 ~(m3c/m2)/metal2 1 ~(m3c/m2)/metal2 (~(m3c/m2),m3c/m2)/metal2 1 \ + "Contact not rectangular (Magic rule)" + + edge4way gv3 ~(gv3)/via3 1 ~(gv3)/via3 (~(gv3),gv3)/via3 1 \ + "Contact not rectangular (Magic rule)" + + edge4way m4c/m3 ~(m4c/m3)/metal3 1 ~(m4c/m3)/metal3 (~(m4c/m3),m4c/m3)/metal3 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,pc/a,gc + + edge4way pad ~(pad)/m4 1 ~(pad)/m4 (~(pad),pad)/m4 1 \ + "Contact not rectangular (Magic rule)" + + exact_overlap ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1 + + exact_overlap m2c/m2 + + exact_overlap m3c/m3 + + exact_overlap m4c/m4 + + exact_overlap gv1 + + exact_overlap gv2 + + exact_overlap gv3 + + edge4way nfet,pfet,fet ~(nfet,pfet,fet)/active 1 ~(nfet,pfet,fet)/active nfet,pfet,fet 1 \ + "Transistor cannot bend in this process (Mosis #?.?)" + + width m1p 4 \ + "Metal1 PIN width < 4 (do_pins)" + + spacing m1p m1p 4 touching_ok \ + "Metal1 PIN spacing < 4 (do_pins)" + + width m2p 4 \ + "Metal2 PIN width < 4 (do_pins)" + + spacing m2p m2p 4 touching_ok \ + "Metal2 PIN spacing < 4 (do_pins)" + + width m3p 4 \ + "Metal3 PIN width < 4 (do_pins)" + + spacing m3p m3p 4 touching_ok \ + "Metal3 PIN spacing < 4 (do_pins)" + + width m4p 4 \ + "Metal4 PIN width < 4 (do_pins)" + + spacing m4p m4p 4 touching_ok \ + "Metal4 PIN spacing < 4 (do_pins)" + +#CC cifstyle lambda=0.20(p) +#CC cifwidth CWN 240 \ +#CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" +#CC cifspacing CWN CWN 120 touching_ok \ +#CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" +#CC cifwidth CWP 240 \ +#CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" +#CC cifspacing CWP CWP 120 touching_ok \ +#CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" +#CC cifwidth CSN 60 \ +#CC "generated CIF layer CSN width will be < 3 (';cif see CSN')" +#CC cifspacing CSN CSN 60 touching_ok \ +#CC "generated CIF layer CSN spacing will be < 3 (';cif see CSN')" +#CC cifwidth CSP 60 \ +#CC "generated CIF layer CSP width will be < 3 (';cif see CSP')" +#CC cifspacing CSP CSP 60 touching_ok \ +#CC "generated CIF layer CSP spacing will be < 3 (';cif see CSP')" + + stepsize 400 + +end + +#--------------------------------------------------- +# LEF format definitions +#--------------------------------------------------- + +lef + + ignore PC + ignore CA + + routing m1 metal1 M1 m1 met1 + routing m2 metal2 M2 m2 met2 + routing m3 metal3 M3 m3 met3 + routing m4 metal4 M4 m4 met4 + + contact m2c via1 via V1 v1 + contact m3c via2 V2 v2 + contact m4c via3 V3 v3 + +end + +extract + style TSMC0.35um(tsmc35)from:t11c + cscale 1 + lambda 20 + step 100 + sidehalo 8 + planeorder well 0 + planeorder implant 1 + planeorder select 2 + planeorder active 3 + planeorder metal1 4 + planeorder metal2 5 + planeorder metal3 6 + planeorder metal4 7 + planeorder oxide 8 + planeorder xp 9 + planeorder comment 10 + planeorder contact 11 + planeorder via1 12 + planeorder via2 13 + planeorder via3 14 + planeorder fill 15 + + resist (ndiff,anres,rnd,ndc,nsd,nwsd,nsc,nwsc)/active 3700 + resist (pdiff,apres,rpd,pdc,psd,psc)/active 2800 + resist (nwell)/well 1018000 + resist (rnw,nwr)/active 1018000 + resist (pwell)/well 1 + resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 6000 + resist (pres)/active 6000 + resist (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c,m2c)/metal1 80 + resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 70 + resist (m3,fm3,rm3,m3c,m4c,m4c)/metal3 80 + resist (m4,fm4,rm4,m4c,pad)/metal4 40 + + contact ndc 4 4100 + contact pdc 4 3400 + contact pc 4 4600 + contact m2c 4 1300 + contact m3c 4 1170 + contact m4c 4 1110 + + +#nwell,cwell,pwell + areacap (nwell)/well 2.360 + +#rnw + areacap (rnw,nwr)/active 2.360 + +#ndiff +# MODEL HANDLES THIS: areacap (ndiff,ndc)/active 43.160 +# MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 43.160 +# MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 64.200 +# MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 64.200 + + areacap (rnd,anres)/active 43.160 + overlap (rnd,anres)/active ~space/w 43.160 + perimc (rnd,anres)/active ~(rnd,anres)/active 64.200 + sideoverlap (rnd,anres)/active ~(rnd,anres)/active ~space/w 64.200 + +#pdiff +# MODEL HANDLES THIS: areacap (pdiff,pdc)/active 55.880 +# MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 55.880 +# MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 81.800 +# MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 81.800 + + areacap (rpd,apres)/active 55.880 + overlap (rpd,apres)/active ~space/w 55.880 + perimc (rpd,apres)/active ~(rpd,apres)/active 81.800 + sideoverlap (rpd,apres)/active ~(rpd,apres)/active ~space/w 81.800 + +#rnw + +#poly +# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,anres,rnd,ndc)/active 181.800 +# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,anres,rnd,ndc)/active 55.400 +# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,apres,rpd,pdc)/active 181.160 +# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,apres,rpd,pdc)/active 52.200 + + sidewall (poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active (poly,fp,pres,rp,pc)/active 11.331 + areacap (poly,fp,pres,rp,pc)/active 4.074 + overlap (poly,fp,pres,rp,pc)/active ~space/w 4.074 + perimc (poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active 4.622 + sideoverlap (poly,fp,pres,rp,pc)/active ~(poly,fp,pres,rp,pc)/active ~space/w 4.622 + +#poly2 + +#rnw + +#metal1 + sidewall (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 20.619 + areacap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 1.666 + +#metal1-sub blocked by ~space/a + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 1.666 ~space/a + perimc (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 2.226 + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.226 ~space/a + +#rnw + overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 1.666 + sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 2.226 + +#metal1-diff blocked by + overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 1.640 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 2.226 + overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 1.640 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 2.226 + +#metal1-poly blocked by + overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 1.687 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 2.250 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 2.250 + +#metal2 + sidewall (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m2,fm2,rm2,m2c,m3c)/metal2 23.532 + areacap (m2,fm2,rm2,m3c)/metal2 0.581 + +#metal2-sub blocked by + overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 0.581 ~space/a,~space/m1 + perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 0.836 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 0.836 ~space/a,~space/m1 + overlap (m2,fm2,rm2,m3c)/metal2 rnw,nwr/active 0.581 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw,nwr/active 0.836 ~space/m1 + +#metal2-*diff blocked by ~space/m1 + overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,anres,rnd,ndc)/active 0.720 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,anres,rnd,ndc)/active 0.836 ~space/m1 + overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,apres,rpd,pdc)/active 0.720 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,apres,rpd,pdc)/active 0.836 ~space/m1 + +#metal2-poly blocked by ~space/m1 + overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.583 ~space/m1 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.840 ~space/m1 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 0.840 ~space/m1 + +#M2->M1 + overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 1.844 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 2.432 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 2.432 + +#metal3 + sidewall (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m3,fm3,rm3,m3c,m4c)/metal3 24.216 + areacap (m3,fm3,rm3,m4c)/metal3 0.352 + +#metal3-sub blocked by ~space/a,~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 ~space/w 0.352 ~space/a,~space/m1,~space/m2 + perimc (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 0.514 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 ~space/w 0.514 ~space/a,~space/m1,~space/m2 + +#rnw + overlap (m3,fm3,rm3,m4c)/metal3 rnw,nwr/active 0.352 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 rnw,nwr/active 0.514 ~space/m1,~space/m2 + +#metal3-*diff blocked by ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (ndiff,anres,rnd,ndc)/active 0.520 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (ndiff,anres,rnd,ndc)/active 0.514 ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (pdiff,apres,rpd,pdc)/active 0.520 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (pdiff,apres,rpd,pdc)/active 0.514 ~space/m1,~space/m2 + +#metal3-poly blocked by ~space/m1,~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.352 ~space/m1,~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.516 ~space/m1,~space/m2 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,m4c)/metal3 0.516 ~space/m1,~space/m2 + +#M3->M1 + +#metal3-metal1 blocked by ~space/m2 + overlap (m3,fm3,rm3,m4c)/metal3 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 0.601 ~space/m2 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 0.864 ~space/m2 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (m3,fm3,rm3,m3c,m4c)/metal3 0.864 ~space/m2 + +#M3->M2 + overlap (m3,fm3,rm3,m4c)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 1.844 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 2.430 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,m4c)/metal3 2.430 + +#metal4 + sidewall (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m4,fm4,rm4,m4c,pad)/metal4 64.860 + areacap (m4,fm4,rm4,pad)/metal4 0.235 + +#metal4-sub blocked by ~space/a,~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 ~space/w 0.235 ~space/a,~space/m1,~space/m2,~space/m3 + perimc (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 0.802 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 ~space/w 0.802 ~space/a,~space/m1,~space/m2,~space/m3 + +#rnw + overlap (m4,fm4,rm4,pad)/metal4 rnw,nwr/active 0.235 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 rnw,nwr/active 0.802 ~space/m1,~space/m2,~space/m3 + +#metal4-*diff blocked by ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (ndiff,anres,rnd,ndc)/active 0.400 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (ndiff,anres,rnd,ndc)/active 0.802 ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (pdiff,apres,rpd,pdc)/active 0.400 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (pdiff,apres,rpd,pdc)/active 0.802 ~space/m1,~space/m2,~space/m3 + +#metal4-poly blocked by ~space/m1,~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.271 ~space/m1,~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 0.666 ~space/m1,~space/m2,~space/m3 + sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m4,fm4,rm4,m4c,pad)/metal4 0.666 ~space/m1,~space/m2,~space/m3 + +#M4->M1 + +#metal4-metal1 blocked by ~space/m2,~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 0.359 ~space/m2,~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 1.038 ~space/m2,~space/m3 + sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (m4,fm4,rm4,m4c,pad)/metal4 1.038 ~space/m2,~space/m3 + +#M4->M2 + +#metal4-metal2 blocked by ~space/m3 + overlap (m4,fm4,rm4,pad)/metal4 (m2,fm2,rm2,m2c,m3c)/metal2 0.601 ~space/m3 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m2,fm2,rm2,m2c,m3c)/metal2 1.698 ~space/m3 + sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m4,fm4,rm4,m4c,pad)/metal4 1.698 ~space/m3 + +#M4->M3 + overlap (m4,fm4,rm4,pad)/metal4 (m3,fm3,rm3,m3c,m4c)/metal3 1.844 + sideoverlap (m4,fm4,rm4,m4c,pad)/metal4 ~(m4,fm4,rm4,m4c,pad)/metal4 (m3,fm3,rm3,m3c,m4c)/metal3 4.604 + sideoverlap (m3,fm3,rm3,m3c,m4c)/metal3 ~(m3,fm3,rm3,m3c,m4c)/metal3 (m4,fm4,rm4,m4c,pad)/metal4 4.604 + +#metal5 + +#metal6 + +#metal7 + +#metali + +#fets + + fet pfet pdiff,pdc 2 pfet Vdd! nwell 52 181 + fet pfet pdiff,pdc 1 pfet Vdd! nwell 52 181 + + fet nfet ndiff,ndc 2 nfet Gnd! pwell 55 182 + fet nfet ndiff,ndc 1 nfet Gnd! pwell 55 182 + + fetresis pfet linear 12182 + fetresis pfet saturation 12182 + fetresis nfet linear 3961 + fetresis nfet saturation 3961 + + fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 + fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 + fet nwr nwsd 2 nwellFig1bResistor Gnd! nwell,pwell 0 0 + fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 + fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 + + fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 + fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 + fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 + fet rmetal4 metal4 2 metal4Resistor Gnd! nwell,pwell 0 0 + + fet pres poly,pc 2 presResistor Gnd! nwell,pwell 0 0 + fet anres ndiff,ndc 2 anresResistor Gnd! nwell,pwell 0 0 + fet apres pdiff,pdc 2 apresResistor Gnd! nwell,pwell 0 0 + +end + +wiring + contact pdcontact 4 metal1 0 pdiff 0 + contact ndcontact 4 metal1 0 ndiff 0 + contact pcontact 4 metal1 0 poly 0 + contact m2contact 4 metal1 0 metal2 0 + contact m3contact 5 metal2 0 metal3 1 + contact m4contact 4 metal3 0 metal4 0 + +end + +router + layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,pres,rp,ndiff,anres,rnd,nsd,nwsd,pdiff,apres,rpd,psd,m1,fm1,rm1 1 + layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 + contacts m2contact 4 + gridspacing 8 + +end + +plowing + fixed nfet,pfet,glass,pad + covered nfet,pfet + drag nfet,pfet + +end + +plot +style colorversatec + ndiff,anres,rnd,ndc/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + ndiff,anres,rnd,ndc/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + nsd,nwsd,nsc/a,nwsc/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + nsd,nwsd,nsc/a,nwsc/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + pdiff,apres,rpd,pdc/a yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + pdiff,apres,rpd,pdc/a cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + pdiff,apres,rpd,pdc/a magenta \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + psd,psc/a yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + psd,psc/a cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + psd,psc/a magenta \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 + poly,fp,pres,rp,pc/a magenta \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + nfet yellow \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 + nfet cyan \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 + nfet magenta \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A + pfet yellow \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 + pfet cyan \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 + pfet magenta \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 + m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 cyan \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + m2,fm2,rm2,m2c/m2,m3c/m2 cyan \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 + m2,fm2,rm2,m2c/m2,m3c/m2 magenta \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 + m2c/m1,gv1 black \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 + pad,glass black \ + 0300 0700 0E00 1C00 \ + 3800 7000 E000 C000 \ + 00C0 00E0 0070 0038 \ + 001C 000E 0007 0003 + nwell yellow \ + 0800 1000 2000 4000 \ + 8000 0001 0002 0004 \ + 0008 0010 0020 0040 \ + 0080 0010 0200 0400 + nwell cyan \ + 1000 2000 4000 8000 \ + 0001 0002 0004 0008 \ + 0010 0020 0040 0080 \ + 0100 0200 0400 0800 + pwell yellow \ + 1000 0400 0400 0100 \ + 0100 0040 0040 0010 \ + 0010 0004 0004 0001 \ + 0001 4000 4000 1000 + pwell cyan \ + 0000 0800 0000 0200 \ + 0000 0080 0000 0020 \ + 0000 0008 0000 0002 \ + 0000 8000 0000 2000 + pwell magenta \ + 0800 0000 0200 0000 \ + 0080 0000 0020 0000 \ + 0008 0000 0002 0000 \ + 8000 0000 2000 0000 + m3c/m2,gv2 black \ + 0100 0000 0000 0000 \ + 1010 0000 0000 0000 \ + 0001 0000 0000 0000 \ + 1010 0000 0000 0000 + m3c/m2,gv2 cyan \ + 0280 0000 0820 0000 \ + 2008 0000 8002 0000 \ + 8002 0000 2008 0000 \ + 0820 0000 0280 0000 + m3c/m2,gv2 magenta \ + 0100 06C0 0440 1830 \ + 1010 600C 4004 8003 \ + 0001 C006 4004 3018 \ + 1010 0C60 0440 0380 + m3c/m2,gv2 black \ + 0820 0820 0820 0FE0 \ + E00F 2008 2008 2008 \ + 2008 2008 2008 E00F \ + 0000 0FE0 0820 0820 + error_p,error_s,error_ps black \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 + magnet yellow \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 + fence magenta \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 + rotate cyan \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc X + +style versatec + pfet \ + 07c0 0f80 1f00 3e00 \ + 7c00 f800 f001 e003 \ + c007 800f 001f 003e \ + 00c7 00f8 01f0 03e0 + nfet \ + 1f00 0f80 07c0 03e0 \ + 01f0 00f8 007c 003e \ + 001f 800f c007 e003 \ + f001 f800 7c00 3e00 + gv1 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 + pwell \ + 2020 2020 2020 2020 \ + 2020 2020 2020 2020 \ + 0000 0000 0000 0000 \ + 0000 0000 0000 0000 + nwell \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 + poly,fp,pres,rp,pc/a,nfet,pfet \ + 0808 0400 0202 0101 \ + 8080 4000 2020 1010 \ + 0808 0004 0202 0101 \ + 8080 0040 2020 1010 + m1,fm1,rm1,ndc/m1,nsc/m1,nwsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 + pad,glass \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 + nsd,nwsd,nsc/a,nwsc/a \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 + m2,fm2,rm2,m2c/m2,m3c/m2 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 + pdiff,apres,rpd,pdc/a,pfet \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 + psd,psc/a \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 + ndiff,anres,rnd,ndc/a,nfet \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc X + +style gremlin + pfet 9 + nfet 10 + gv1 11 + pwell 15 + nwell 16 + poly,fp,pres,rp,pc/a,nfet,pfet 19 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc 22 + pad,glass 23 + nsd,nwsd,nsc/a,nwsc/a 24 + gv1 28 + pdiff,apres,rpd,pdc/a,pfet 29 + psd,psc/a 30 + ndiff,anres,rnd,ndc/a,nfet 31 + pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc,gv1 X + +end + diff --git a/technology/scn4m_subm/tech/__init__.py b/technology/scn4m_subm/tech/__init__.py new file mode 100755 index 00000000..6b2d03b3 --- /dev/null +++ b/technology/scn4m_subm/tech/__init__.py @@ -0,0 +1,6 @@ +""" +Import tech specific modules. +""" + +from tech import * + diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py new file mode 100755 index 00000000..fc7440e1 --- /dev/null +++ b/technology/scn4m_subm/tech/tech.py @@ -0,0 +1,293 @@ +import os + +""" +File containing the process technology parameters for SCMOS 3me, subm, 180nm. +""" + +info={} +info["name"]="scn3me_subm" +info["body_tie_down"] = 0 +info["has_pwell"] = True +info["has_nwell"] = True + +#GDS file info +GDS={} +# gds units +GDS["unit"]=(0.001,1e-6) +# default label zoom +GDS["zoom"] = 0.5 + + +################################################### +##GDS Layer Map +################################################### + +# create the GDS layer map +layer={} +layer["vtg"] = -1 +layer["vth"] = -1 +layer["contact"] = 47 +layer["pwell"] = 41 +layer["nwell"] = 42 +layer["active"] = 43 +layer["pimplant"] = 44 +layer["nimplant"] = 45 +layer["poly"] = 46 +layer["active_contact"] = 48 +layer["metal1"] = 49 +layer["via1"] = 50 +layer["metal2"] = 51 +layer["via2"] = 61 +layer["metal3"] = 62 +layer["via3"] = 30 +layer["metal4"] = 31 +layer["text"] = 63 +layer["boundary"] = 63 +layer["blockage"] = 83 + +################################################### +##END GDS Layer Map +################################################### + +################################################### +##DRC/LVS Rules Setup +################################################### +_lambda_ = 0.2 + +#technology parameter +parameter={} +parameter["min_tx_size"] = 4*_lambda_ +parameter["beta"] = 2 + +drclvs_home=os.environ.get("DRCLVS_HOME") + +drc={} +#grid size is 1/2 a lambda +drc["grid"]=0.5*_lambda_ +#DRC/LVS test set_up +drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" +drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" +drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" + + +# minwidth_tx with contact (no dog bone transistors) +drc["minwidth_tx"] = 4*_lambda_ +drc["minlength_channel"] = 2*_lambda_ + +# 1.3 Minimum spacing between wells of same type (if both are drawn) +drc["well_to_well"] = 6*_lambda_ +# 1.4 Minimum spacing between wells of different type (if both are drawn) +drc["pwell_to_nwell"] = 0 +# 1.1 Minimum width +drc["minwidth_well"] = 12*_lambda_ + +# 3.1 Minimum width +drc["minwidth_poly"] = 2*_lambda_ +# 3.2 Minimum spacing over active +drc["poly_to_poly"] = 3*_lambda_ +# 3.3 Minimum gate extension of active +drc["poly_extend_active"] = 2*_lambda_ +# 5.5.b Minimum spacing between poly contact and other poly (alternative rules) +drc["poly_to_polycontact"] = 4*_lambda_ +# ?? +drc["active_enclosure_gate"] = 0.0 +# 3.5 Minimum field poly to active +drc["poly_to_active"] = _lambda_ +# 3.2.a Minimum spacing over field poly +drc["poly_to_field_poly"] = 3*_lambda_ +# Not a rule +drc["minarea_poly"] = 0.0 + +# ?? +drc["active_to_body_active"] = 4*_lambda_ # Fix me +# 2.1 Minimum width +drc["minwidth_active"] = 3*_lambda_ +# 2.2 Minimum spacing +drc["active_to_active"] = 3*_lambda_ +# 2.3 Source/drain active to well edge +drc["well_enclosure_active"] = 6*_lambda_ +# Reserved for asymmetric enclosures +drc["well_extend_active"] = 6*_lambda_ +# Not a rule +drc["minarea_active"] = 0.0 + +# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width +drc["implant_to_channel"] = 3*_lambda_ +# 4.2 Minimum select overlap of active +drc["implant_enclosure_active"] = 2*_lambda_ +# 4.3 Minimum select overlap of contact +drc["implant_enclosure_contact"] = _lambda_ +# Not a rule +drc["implant_to_contact"] = 0 +# Not a rule +drc["implant_to_implant"] = 0 +# Not a rule +drc["minwidth_implant"] = 0 + +# 6.1 Exact contact size +drc["minwidth_contact"] = 2*_lambda_ +# 5.3 Minimum contact spacing +drc["contact_to_contact"] = 3*_lambda_ +# 6.2.b Minimum active overlap +drc["active_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["active_extend_contact"] = _lambda_ +# 5.2.b Minimum poly overlap +drc["poly_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosures +drc["poly_extend_contact"] = _lambda_ +# Reserved for other technologies +drc["contact_to_gate"] = 2*_lambda_ +# 5.4 Minimum spacing to gate of transistor +drc["contact_to_poly"] = 2*_lambda_ + +# 7.1 Minimum width +drc["minwidth_metal1"] = 3*_lambda_ +# 7.2 Minimum spacing +drc["metal1_to_metal1"] = 3*_lambda_ +# 7.3 Minimum overlap of any contact +drc["metal1_enclosure_contact"] = _lambda_ +# Reserved for asymmetric enclosure +drc["metal1_extend_contact"] = _lambda_ +# 8.3 Minimum overlap by metal1 +drc["metal1_enclosure_via1"] = _lambda_ +# Reserve for asymmetric enclosures +drc["metal1_extend_via1"] = _lambda_ +# Not a rule +drc["minarea_metal1"] = 0 + +# 8.1 Exact size +drc["minwidth_via1"] = 2*_lambda_ +# 8.2 Minimum via1 spacing +drc["via1_to_via1"] = 3*_lambda_ + +# 9.1 Minimum width +drc["minwidth_metal2"] = 3*_lambda_ +# 9.2 Minimum spacing +drc["metal2_to_metal2"] = 3*_lambda_ +# 9.3 Minimum overlap of via1 +drc["metal2_extend_via1"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal2_enclosure_via1"] = _lambda_ +# 14.3 Minimum overlap by metal2 +drc["metal2_extend_via2"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal2_enclosure_via2"] = _lambda_ +# Not a rule +drc["minarea_metal2"] = 0 + +# 14.1 Exact size +drc["minwidth_via2"] = 2*_lambda_ +# 14.2 Minimum spacing +drc["via2_to_via2"] = 3*_lambda_ + +# 15.1 Minimum width +drc["minwidth_metal3"] = 3*_lambda_ +# 15.2 Minimum spacing to metal3 +drc["metal3_to_metal3"] = 3*_lambda_ +# 15.3 Minimum overlap of via 2 +drc["metal3_extend_via2"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal3_enclosure_via2"] = _lambda_ +# 21.3 Minimum overlap by metal3 +drc["metal3_extend_via3"] = _lambda_ +# Reserved for asymmetric enclosures +drc["metal3_enclosure_via3"] = _lambda_ +# Not a rule +drc["minarea_metal3"] = 0 + +# 21.1 Exact size +drc["minwidth_via3"] = 2*_lambda_ +# 21.2 Minimum spacing +drc["via3_to_via3"] = 3*_lambda_ + +# 22.1 Minimum width +drc["minwidth_metal4"] = 6*_lambda_ +# 22.2 Minimum spacing to metal4 +drc["metal4_to_metal4"] = 6*_lambda_ +# 22.3 Minimum overlap of via 3 +drc["metal4_extend_via3"] = 2*_lambda_ +# Reserved for asymmetric enclosures +drc["metal4_enclosure_via3"] = 2*_lambda_ +# Not a rule +drc["minarea_metal4"] = 0 + +################################################### +##END DRC/LVS Rules +################################################### + +################################################### +##Spice Simulation Parameters +################################################### + +# spice model info +spice={} +spice["nmos"]="n" +spice["pmos"]="p" +# This is a map of corners to model files +SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR") +# FIXME: Uncomment when we have the new spice models +#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] } +spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], + "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], + "SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + "SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"] } + + +#spice stimulus related variables +spice["feasible_period"] = 5 # estimated feasible period in ns +spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts] +spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts] +spice["rise_time"] = 0.05 # rise time in [Nano-seconds] +spice["fall_time"] = 0.05 # fall time in [Nano-seconds] +spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius) +spice["nom_temperature"] = 25 # Nominal temperature (celcius) + +#sram signal names +#FIXME: We don't use these everywhere... +spice["vdd_name"] = "vdd" +spice["gnd_name"] = "gnd" +spice["control_signals"] = ["CSB", "WEB"] +spice["data_name"] = "DATA" +spice["addr_name"] = "ADDR" +spice["minwidth_tx"] = drc["minwidth_tx"] +spice["channel"] = drc["minlength_channel"] +spice["clk"] = "clk" + +# analytical delay parameters +# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45. +spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square +spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2 +spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms +spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff +spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff +spice["msflop_setup"] = 9 # DFF setup time in ps +spice["msflop_hold"] = 1 # DFF hold time in ps +spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] +spice["dff_setup"] = 9 # DFF setup time in ps +spice["dff_hold"] = 1 # DFF hold time in ps +spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps +spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load +spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] + +# analytical power parameters, many values are temporary +spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW +spice["inv_leakage"] = 1 # Leakage power of inverter in nW +spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW +spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW +spice["msflop_leakage"] = 1 # Leakage power of flop in nW +spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF + +spice["default_event_rate"] = 100 # Default event activity of every gate. MHz +spice["flop_transition_prob"] = .5 # Transition probability of inverter. +spice["inv_transition_prob"] = .5 # Transition probability of inverter. +spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. +spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. +spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. +################################################### +##END Spice Simulation Parameters +################################################### diff --git a/technology/scn4m_subm/tf/LICENSE b/technology/scn4m_subm/tf/LICENSE new file mode 100644 index 00000000..8d22c4be --- /dev/null +++ b/technology/scn4m_subm/tf/LICENSE @@ -0,0 +1,4 @@ +The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, +2006. Users are free to use or modify the NCSU CDK as appropriate as long +as this notice appears in the modified package. The NCSU CDK is +provided with NO WARRANTY. diff --git a/technology/scn4m_subm/tf/README b/technology/scn4m_subm/tf/README new file mode 100644 index 00000000..d2531fe1 --- /dev/null +++ b/technology/scn4m_subm/tf/README @@ -0,0 +1,21 @@ +;; NCSU CDK v. 1.6.0.beta +;; Last Modified: 2007-07-12 + +The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, +2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long +as this notice appears in the modified package. The NCSU CDK is +provided with NO WARRANTY. + +As of version 1.5.1, all documentation for the NCSU CDK is provided +by the NCSU EDA Wiki which can be found at: + + http://www.eda.ncsu.edu/ + +This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1 +for OpenAccess. Details of the conversion of the CDK from the CDB version can +be found in the file cdb2oa/OA_Conversion.txt. + +This kit is not yet fully supported. Please post problems and solutions at +http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1 + +Modified 2018 by MRG to contain SCN4ME Via3/Metal4 layers. \ No newline at end of file diff --git a/technology/scn4m_subm/tf/display.drf b/technology/scn4m_subm/tf/display.drf new file mode 100644 index 00000000..aeeefe2c --- /dev/null +++ b/technology/scn4m_subm/tf/display.drf @@ -0,0 +1,717 @@ +drDefineDisplay( +;( DisplayName ) + ( display ) +) +drDefineColor( +;( DisplayName ColorsName Red Green Blue ) + ( display white 255 255 255 ) + ( display yellow 255 255 0 ) + ( display silver 217 230 255 ) + ( display cream 255 255 204 ) + ( display pink 255 191 242 ) + ( display magenta 255 0 255 ) + ( display lime 0 255 0 ) + ( display tan 255 230 191 ) + ( display cyan 0 255 255 ) + ( display cadetBlue 57 191 255 ) + ( display orange 255 128 0 ) + ( display red 255 51 51 ) + ( display purple 153 0 230 ) + ( display green 0 204 102 ) + ( display brown 191 64 38 ) + ( display blue 51 77 255 ) + ( display slate 140 140 166 ) + ( display gold 217 204 0 ) + ( display maroon 230 31 13 ) + ( display violet 94 0 230 ) + ( display forest 38 140 107 ) + ( display chocolate 128 38 38 ) + ( display navy 51 51 153 ) + ( display black 0 0 0 ) + ( display gray 204 204 217 ) + ( display winColor1 166 166 166 ) + ( display winColor2 115 115 115 ) + ( display winColor3 189 204 204 ) + ( display winColor4 204 204 204 ) + ( display winColor5 199 199 199 ) + ( display blinkRed 255 0 0 t ) + ( display blinkYellow 255 255 0 t ) + ( display blinkWhite 255 255 255 t ) + ( display winBack 224 224 224 ) + ( display winFore 128 0 0 ) + ( display winText 51 51 51 ) +) +drDefineStipple( +;( DisplayName StippleName Bitmap ) + ( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) + ( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) ) + ( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) ) + ( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 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0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) + ( display backSlash ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) + ( display hZigZag ( ( 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 ) + ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ) + ( 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 ) + ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ) + ( 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 ) + ( 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 ) + ( 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 ) + ( 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ) ) ) + ( display vZigZag ( ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ) + ( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 ) + ( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ) + ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ) + ( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) + ( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 ) + ( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 ) + ( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 ) + ( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ) ) ) + ( display hCurb ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display vCurb ( ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 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0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) + ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) ) ) + ( display triangle ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 ) + ( 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display x ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) ) + ( display stipple0 ( ( 1 ) ) ) + ( display stipple1 ( ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display stipple2 ( ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) + ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) + ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) ) ) + ( display stipple3 ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) + ( display stipple4 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) ) ) + ( display stipple5 ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) + ( display stipple6 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) + ( display stipple7 ( ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) + ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) + ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) + ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) + ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) + ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) + ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) ) ) + ( display stipple8 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) + ( display stipple9 ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) + ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) ) + ( display stipple10 ( ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display stipple11 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) + ( display dots2 ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) + ( display dots4 ( ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) ) ) + ( display dats5 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) + ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) +) +drDefineLineStyle( +;( DisplayName LineStyle Size Pattern ) + ( display solid 1 (1 ) ) + ( display dashed 1 (1 1 1 0 0 1 1 1 ) ) + ( display dots 1 (1 0 0 ) ) + ( display dashDot 1 (1 1 1 0 0 1 0 0 ) ) + ( display shortDash 1 (1 1 0 0 ) ) + ( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0 ) ) + ( display hidden 1 (1 0 0 0 ) ) + ( display thickLine 3 (1 1 1 ) ) + ( display lineStyle0 1 (1 ) ) + ( display lineStyle1 1 (1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 ) ) +) +drDefinePacket( +;( DisplayName PacketName Stipple LineStyle Fill Outline [FillStyle]) + ( display NwellNet dots4 thickLine slate slate outlineStipple) + ( display border stipple0 solid tan tan solid ) + ( display y8 stipple0 solid gold gold solid ) + ( display background stipple1 lineStyle0 black black outlineStipple) + ( display y9 stipple0 solid silver silver solid ) + ( display Metal3Net dots4 solid navy navy outlineStipple) + ( display Metal3Net dots4 solid tan tan outlineStipple) + ( display A1 stipple0 lineStyle0 winBack winBack solid ) + ( display pin solid lineStyle0 red red solid ) + ( display XPNet blank solid yellow yellow outline ) + ( display hardFence stipple0 solid red red solid ) + ( display PbaseNet dots4 solid yellow yellow outlineStipple) + ( display designFlow3 stipple1 lineStyle0 pink pink outlineStipple) + ( display A2 stipple0 lineStyle0 winBack winBack solid ) + ( display Unrouted1 stipple0 lineStyle1 brown brown solid ) + ( display RowLbl blank solid cyan cyan outline ) + ( display edgeLayerPin stipple0 solid yellow yellow solid ) + ( display instance blank solid winBack red outline ) + ( display Nselect dots4 solid green green outlineStipple) + ( display snap stipple0 solid yellow yellow solid ) + ( display pinAnt stipple0 solid red red solid ) + ( display winAttentionText solid solid winText winText solid ) + ( display designFlow2 stipple1 lineStyle0 purple purple outlineStipple) + ( display Unrouted2 stipple0 lineStyle1 red red solid ) + ( display hilite blank solid white white outline ) + ( display P2Con solid lineStyle0 orange orange solid ) + ( display designFlow1 stipple1 lineStyle0 red red outlineStipple) + ( display grid1 stipple0 solid gray gray solid ) + ( display Unrouted3 stipple0 lineStyle1 pink pink solid ) + ( display ViaNet x solid magenta magenta outlineStipple) + ( display select stipple0 solid tan tan solid ) + ( display Poly2Net dots4 lineStyle0 orange orange outlineStipple) + ( display winText solid solid winText winText solid ) + ( display Unrouted4 stipple0 lineStyle1 orange orange solid ) + ( display wireLbl solid lineStyle0 cyan cyan solid ) + ( display designFlow7 stipple1 lineStyle0 cyan cyan outlineStipple) + ( display align stipple0 solid tan tan solid ) + ( display Poly2Pin blank solid yellow yellow outline ) + ( display Unrouted5 stipple0 lineStyle1 green green solid ) + ( display unset stipple0 solid forest forest solid ) + ( display Poly1Net dots4 lineStyle0 red red outlineStipple) + ( display Resistor dots2 lineStyle0 cyan cyan outlineStipple) + ( display DiodeNet dots4 lineStyle0 cream cream outlineStipple) + ( display designFlow6 stipple1 lineStyle0 tan tan outlineStipple) + ( display Unrouted6 stipple0 lineStyle1 blue blue solid ) + ( display resist stipple0 solid cyan cyan solid ) + ( display designFlow5 stipple1 lineStyle0 silver silver outlineStipple) + ( display CapWellNet brick solid slate slate outlineStipple) + ( display Unrouted7 stipple0 lineStyle1 purple purple solid ) + ( display CannotoccupyBnd blank solid red red outline ) + ( display winTopShadow solid solid white white solid ) + ( display designFlow4 stipple1 lineStyle0 black black outlineStipple) + ( display softFence stipple0 solid yellow yellow solid ) + ( display ResistorNet dots4 solid cyan cyan outlineStipple) + ( display winError solid solid winColor5 winColor5 solid ) + ( display changedLayerTl1 stipple0 solid yellow yellow solid ) + ( display prBoundaryLbl stipple0 solid purple purple solid ) + ( display ActXNet x solid yellow yellow outlineStipple) + ( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple) + ( display Active dots2 lineStyle0 yellow yellow outlineStipple) + ( display changedLayerTl0 stipple0 solid red red solid ) + ( display spike stipple0 solid purple purple solid ) + ( display Metal3 grid solid navy violet outlineStipple) + ( display Metal4 grid solid tan tan outlineStipple) + ( display text blank solid white white outline ) + ( display Poly1Pin stipple0 lineStyle0 red red solid ) + ( display Row blank solid cyan cyan outline ) + ( display Pwell stipple9 lineStyle0 slate slate outlineStipple) + ( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple) + ( display wire solid lineStyle0 cyan cyan solid ) + ( display ActX solid solid yellow yellow solid ) + ( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple) + ( display Cannotoccupy blank solid red red outline ) + ( display GroupLbl stipple0 solid green green solid ) + ( display axis stipple0 solid slate slate solid ) + ( display SiBlockNet x dashed tan tan outlineStipple) + ( display edgeLayer stipple0 solid gray gray solid ) + ( display annotate2 stipple0 solid lime lime solid ) + ( display Metal1Pin stipple0 lineStyle0 blue blue solid ) + ( display Diode stipple7 lineStyle0 cream cream outlineStipple) + ( display Glass X lineStyle0 white white X ) + ( display ViaXNet x solid magenta magenta outlineStipple) + ( display annotate3 stipple0 solid cyan cyan solid ) + ( display Poly2 dots1 lineStyle0 orange orange outlineStipple) + ( display deviceAnt stipple0 solid yellow yellow solid ) + ( display winBottomShadow solid solid winColor1 winColor1 solid ) + ( display PselectNet dots4 solid brown brown outlineStipple) + ( display comment stipple0 lineStyle0 winBack winBack outline ) + ( display Poly1 dots lineStyle0 red red outlineStipple) + ( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid ) + ( display stretch stipple0 solid yellow yellow solid ) + ( display XP blank lineStyle0 winBack gold outline ) + ( display annotate1 stipple0 solid pink pink solid ) + ( display Group stipple2 solid green green outlineStipple) + ( display deviceLbl stipple0 solid green green solid ) + ( display annotate6 stipple0 solid silver silver solid ) + ( display GlassNet blank solid yellow yellow outline ) + ( display Canplace blank solid cyan cyan outline ) + ( display annotate7 stipple0 solid red red solid ) + ( display Via2 solid solid navy navy solid ) + ( display Metal2Pin stipple0 lineStyle0 magenta magenta solid ) + ( display annotate4 stipple0 solid yellow yellow solid ) + ( display device1 stipple1 lineStyle0 green green outlineStipple) + ( display "90" blank solid white white outline ) + ( display markerWarn x solid yellow yellow outlineStipple) + ( display text2 stipple1 lineStyle0 white white outlineStipple) + ( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple) + ( display designFlow stipple1 lineStyle0 green green outlineStipple) + ( display hilite1 stipple0 solid silver silver solid ) + ( display device blank solid green green outline ) + ( display prBoundary stipple0 solid purple purple solid ) + ( display annotate5 stipple0 solid white white solid ) + ( display text1 stipple0 dashed white white solid ) + ( display Via solid solid magenta magenta solid ) + ( display Capacitor stipple7 lineStyle0 tan tan outlineStipple) + ( display markerErr x solid white white outlineStipple) + ( display unknown stipple0 solid yellow yellow solid ) + ( display annotate stipple0 solid orange orange solid ) + ( display P1ConNet x solid red red outlineStipple) + ( display hilite3 stipple0 solid cyan cyan solid ) + ( display winActiveBanner solid solid winColor3 winColor3 solid ) + ( display pinLbl stipple0 solid red red solid ) + ( display device2 stipple0 lineStyle1 green green solid ) + ( display grid stipple0 solid slate slate solid ) + ( display winBackground solid solid winBack winBack solid ) + ( display Metal1Net dots4 lineStyle0 blue blue outlineStipple) + ( display hilite2 stipple0 solid tan tan solid ) + ( display annotate8 stipple0 solid tan tan solid ) + ( display hilite5 stipple0 solid lime lime solid ) + ( display annotate9 stipple0 solid green green solid ) + ( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple) + ( display Metal3Pin stipple0 solid navy navy solid ) + ( display Metal4Pin stipple0 solid tan tan solid ) + ( display hilite4 stipple0 solid gray gray solid ) + ( display y0 stipple0 solid gray gray solid ) + ( display supply stipple0 solid lime lime solid ) + ( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple) + ( display hilite7 stipple0 solid cream cream solid ) + ( display y1 stipple0 solid brown brown solid ) + ( display defaultPacket x solid chocolate winColor2 outlineStipple) + ( display Via2Net cross solid navy navy outlineStipple) + ( display NselectNet dots4 solid green green outlineStipple) + ( display Unrouted8 stipple0 lineStyle1 gold gold solid ) + ( display hilite6 stipple0 solid orange orange solid ) + ( display y2 stipple0 solid red red solid ) + ( display winBorder solid solid winColor2 winColor2 solid ) + ( display Nwell dats5 thickLine slate slate outlineStipple) + ( display Unrouted9 stipple0 lineStyle1 silver silver solid ) + ( display hilite9 stipple0 solid pink pink solid ) + ( display SiBlock blank dashed tan tan outline ) + ( display y3 stipple0 solid orange orange solid ) + ( display prBoundaryBnd stipple0 solid cyan cyan solid ) + ( display winForeground solid solid winFore winFore solid ) + ( display hilite8 stipple0 solid magenta magenta solid ) + ( display y4 stipple0 solid yellow yellow solid ) + ( display Pselect dots1 solid brown brown outlineStipple) + ( display winInactiveBanner solid solid winColor4 winColor4 solid ) + ( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple) + ( display winButton solid solid winFore winFore solid ) + ( display y5 stipple0 solid green green solid ) + ( display hiz stipple0 solid orange orange solid ) + ( display drive stipple0 solid blue blue solid ) + ( display wireFlt stipple0 dashed red red solid ) + ( display instanceLbl stipple0 solid gold gold solid ) + ( display P2ConNet x lineStyle0 orange orange outlineStipple) + ( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple) + ( display y6 stipple0 solid blue blue solid ) + ( display PwellNet dots4 lineStyle0 slate slate outlineStipple) + ( display P1Con solid solid red red solid ) + ( display CapWell dagger solid slate slate outlineStipple) + ( display y7 stipple0 solid purple purple solid ) + ( display ViaX solid solid magenta magenta solid ) + ( display HR x solid chocolate winColor2 outlineStipple) + ( display HRnet x solid chocolate winColor2 outlineStipple) +) diff --git a/technology/scn4m_subm/tf/glade_scn4me_subm.py b/technology/scn4m_subm/tf/glade_scn4me_subm.py new file mode 100644 index 00000000..d2f9aa7e --- /dev/null +++ b/technology/scn4m_subm/tf/glade_scn4me_subm.py @@ -0,0 +1,7 @@ +import os +CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf" +ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map") + + + + diff --git a/technology/scn3me_subm/layers.map b/technology/scn4m_subm/tf/layers.map similarity index 83% rename from technology/scn3me_subm/layers.map rename to technology/scn4m_subm/tf/layers.map index d10d5f2d..80b659d9 100644 --- a/technology/scn3me_subm/layers.map +++ b/technology/scn4m_subm/tf/layers.map @@ -12,5 +12,7 @@ Via drawing 50 0 Metal2 drawing 51 0 Via2 drawing 61 0 Metal3 drawing 62 0 +Via3 drawing 30 0 +Metal4 drawing 31 0 Glass drawing 52 0 -text drawing 83 0 +comment drawing 63 0 diff --git a/technology/scn4m_subm/tf/mosis.tf b/technology/scn4m_subm/tf/mosis.tf new file mode 100644 index 00000000..e48d76a0 --- /dev/null +++ b/technology/scn4m_subm/tf/mosis.tf @@ -0,0 +1,850 @@ +; Generated on Sep 28 16:05:23 1998 +; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $ +; +; Matt Clapp fixed: October 10, 2002 +; added via devices, deleted useless app-specific crap, +; added lxExtractRules so undo in layout editor doesn't +; complain. + + +;******************************** +; LAYER DEFINITION +;******************************** + +layerDefinitions( + techLayers( + ;( LayerName Layer# Abbreviation ) + ;( --------- ------ ------------ ) + ;User-Defined Layers: + ( P2Con 3 P2Con ) + ( Poly2 7 Poly2 ) + ( Pbase 10 Pbase ) + ( Resistor 16 Resisto ) + ( Capacitor 17 Capacit ) + ( Diode 18 Diode ) + ( SiBlock 29 SiBlock ) + ( HR 34 HR ) + ( Pwell 41 Pwell ) + ( Nwell 42 Nwell ) + ( Active 43 Active ) + ( Pselect 44 Pselect ) + ( Nselect 45 Nselect ) + ( Poly1 46 Poly1 ) + ( P1Con 47 P1Con ) + ( ActX 48 ActX ) + ( Metal1 49 Metal1 ) + ( Via 50 Via ) + ( Metal2 51 Metal2 ) + ( Glass 52 Glass ) + ( CapWell 59 CapWell ) + ( XP 60 XP ) + ( Via2 61 Via2 ) + ( Metal3 62 Metal3 ) + ( Via3 30 Via3 ) + ( Metal4 31 Metal4 ) + ( A1 80 A1 ) + ( A2 81 A2 ) + ( comment 117 comment ) + ;System-Reserved Layers: + ( Unrouted 200 Unroute ) + ( Row 201 Row ) + ( Group 202 Group ) + ( Cannotoccupy 203 Cannoto ) + ( Canplace 204 Canplac ) + ( hardFence 205 hardFen ) + ( softFence 206 softFen ) + ( y0 207 y0 ) + ( y1 208 y1 ) + ( y2 209 y2 ) + ( y3 210 y3 ) + ( y4 211 y4 ) + ( y5 212 y5 ) + ( y6 213 y6 ) + ( y7 214 y7 ) + ( y8 215 y8 ) + ( y9 216 y9 ) + ( designFlow 217 designF ) + ( stretch 218 stretch ) + ( edgeLayer 219 edgeLay ) + ( changedLayer 220 changed ) + ( unset 221 unset ) + ( unknown 222 unknown ) + ( spike 223 spike ) + ( hiz 224 hiz ) + ( resist 225 resist ) + ( drive 226 drive ) + ( supply 227 supply ) + ( wire 228 wire ) + ( pin 229 pin ) + ( text 230 text ) + ( device 231 device ) + ( border 232 border ) + ( snap 233 snap ) + ( align 234 align ) + ( prBoundary 235 prBound ) + ( instance 236 instanc ) + ( annotate 237 annotat ) + ( marker 238 marker ) + ( select 239 select ) + ( grid 251 grid ) + ( axis 252 axis ) + ( hilite 253 hilite ) + ( background 254 backgro ) + ) ;techLayers + + techPurposes( + ;( PurposeName Purpose# Abbreviation ) + ;( ----------- -------- ------------ ) + ;User-Defined Purposes: + ;System-Reserved Purposes: + ( warning 234 wng ) + ( tool1 235 tl1 ) + ( tool0 236 tl0 ) + ( label 237 lbl ) + ( flight 238 flt ) + ( error 239 err ) + ( annotate 240 ant ) + ( drawing1 241 dr1 ) + ( drawing2 242 dr2 ) + ( drawing3 243 dr3 ) + ( drawing4 244 dr4 ) + ( drawing5 245 dr5 ) + ( drawing6 246 dr6 ) + ( drawing7 247 dr7 ) + ( drawing8 248 dr8 ) + ( drawing9 249 dr9 ) + ( boundary 250 bnd ) + ( pin 251 pin ) + ( drawing 252 drw ) + ( net 253 net ) + ( cell 254 cel ) + ( all 255 all ) + ) ;techPurposes + + techLayerPurposePriorities( + ;layers are ordered from lowest to highest priority + ; (higher priority is drawn on top of lower priority) + ;( LayerName Purpose ) + ;( --------- ------- ) + ( background drawing ) + ( grid drawing ) + ( grid drawing1 ) + ( Nwell drawing ) + ( Pwell drawing ) + ( CapWell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( annotate drawing ) + ( annotate drawing1 ) + ( annotate drawing2 ) + ( annotate drawing3 ) + ( annotate drawing4 ) + ( annotate drawing5 ) + ( annotate drawing6 ) + ( annotate drawing7 ) + ( annotate drawing8 ) + ( annotate drawing9 ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Glass drawing ) + ( XP drawing ) + ( prBoundary drawing ) + ( prBoundary boundary ) + ( instance drawing ) + ( prBoundary label ) + ( instance label ) + ( Row drawing ) + ( Nwell net ) + ( align drawing ) + ( Pwell net ) + ( CapWell net ) + ( hardFence drawing ) + ( Active net ) + ( softFence drawing ) + ( Row label ) + ( Group drawing ) + ( Group label ) + ( Cannotoccupy drawing ) + ( Cannotoccupy boundary ) + ( Canplace drawing ) + ( ActX net ) + ( A2 drawing ) + ( A1 drawing ) + ( comment drawing ) + ( border drawing ) + ( Pselect net ) + ( Nselect net ) + ( SiBlock net ) + ( HR net ) + ( wire drawing ) + ( Poly1 net ) + ( wire label ) + ( P1Con net ) + ( wire flight ) + ( Metal1 net ) + ( device annotate ) + ( Metal2 net ) + ( device label ) + ( Via net ) + ( Metal3 net ) + ( Via2 net ) + ( pin label ) + ( text drawing ) + ( pin drawing ) + ( text drawing1 ) + ( pin annotate ) + ( device drawing ) + ( axis drawing ) + ( edgeLayer drawing ) + ( edgeLayer pin ) + ( snap drawing ) + ( stretch drawing ) + ( y0 drawing ) + ( y1 drawing ) + ( y2 drawing ) + ( y3 drawing ) + ( y4 drawing ) + ( y5 drawing ) + ( y6 drawing ) + ( y7 drawing ) + ( y8 drawing ) + ( y9 drawing ) + ( hilite drawing ) + ( hilite drawing1 ) + ( hilite drawing2 ) + ( hilite drawing3 ) + ( hilite drawing4 ) + ( hilite drawing5 ) + ( hilite drawing6 ) + ( hilite drawing7 ) + ( hilite drawing8 ) + ( hilite drawing9 ) + ( select drawing ) + ( drive drawing ) + ( hiz drawing ) + ( resist drawing ) + ( spike drawing ) + ( supply drawing ) + ( unknown drawing ) + ( unset drawing ) + ( designFlow drawing ) + ( designFlow drawing1 ) + ( designFlow drawing2 ) + ( designFlow drawing3 ) + ( designFlow drawing4 ) + ( designFlow drawing5 ) + ( designFlow drawing6 ) + ( designFlow drawing7 ) + ( designFlow drawing8 ) + ( designFlow drawing9 ) + ( changedLayer tool0 ) + ( changedLayer tool1 ) + ( marker warning ) + ( marker error ) + ( device drawing1 ) + ( Pbase drawing ) + ( Pbase net ) + ( Resistor net ) + ( Resistor drawing ) + ( Capacitor net ) + ( Capacitor drawing ) + ( Diode net ) + ( Diode drawing ) + ( Poly2 net ) + ( P2Con net ) + ( device drawing2 ) + ( Unrouted drawing ) + ( text drawing2 ) + ( Unrouted drawing1 ) + ( Unrouted drawing2 ) + ( Unrouted drawing3 ) + ( Unrouted drawing4 ) + ( Unrouted drawing5 ) + ( Unrouted drawing6 ) + ( Unrouted drawing7 ) + ( Unrouted drawing8 ) + ( Unrouted drawing9 ) + ) ;techLayerPurposePriorities + + techDisplays( + ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) + ;( --------- ------- ------ --- --- --------- ------- ----- ) + ( background drawing background t nil nil nil nil ) + ( grid drawing grid t nil nil nil nil ) + ( grid drawing1 grid1 t nil nil nil nil ) + ( Nwell drawing Nwell t t t t t ) + ( Pwell drawing Pwell t t t t nil ) + ( Active drawing Active t t t t t ) + ( ActX drawing ActX t t t t t ) + ( Pselect drawing Pselect t t t t t ) + ( Nselect drawing Nselect t t t t t ) + ( SiBlock drawing SiBlock t t t t t ) + ( HR drawing HR t t t t t ) + ( CapWell drawing CapWell t t t t t ) + ( Poly1 drawing Poly1 t t t t t ) + ( P1Con drawing P1Con t t t t t ) + ( Metal1 drawing Metal1 t t t t t ) + ( Via drawing Via t t t t t ) + ( Metal2 drawing Metal2 t t t t t ) + ( annotate drawing annotate t t nil t nil ) + ( annotate drawing1 annotate1 t t nil t nil ) + ( annotate drawing2 annotate2 t t nil t nil ) + ( annotate drawing3 annotate3 t t nil t nil ) + ( annotate drawing4 annotate4 t t nil t nil ) + ( annotate drawing5 annotate5 t t nil t nil ) + ( annotate drawing6 annotate6 t t nil t nil ) + ( annotate drawing7 annotate7 t t nil t nil ) + ( annotate drawing8 annotate8 t t nil t nil ) + ( annotate drawing9 annotate9 t t nil t nil ) + ( Via2 drawing Via2 t t t t t ) + ( Metal3 drawing Metal3 t t t t t ) + ( Glass drawing Glass t t t nil t ) + ( XP drawing XP t t t nil t ) + ( Metal1 pin Metal1Pin t t t nil t ) + ( Metal2 pin Metal2Pin t t t nil t ) + ( Metal3 pin Metal3Pin t t t nil t ) + ( Poly1 pin Poly1Pin t t t nil t ) + ( prBoundary drawing prBoundary t t nil t nil ) + ( prBoundary boundary prBoundaryBnd t t nil t nil ) + ( instance drawing instance t t nil t t ) + ( prBoundary label prBoundaryLbl t t t t nil ) + ( instance label instanceLbl t t t t nil ) + ( Row drawing Row t t t t nil ) + ( Nwell net NwellNet t t t nil nil ) + ( align drawing align t t nil t nil ) + ( Pwell net PwellNet t t t nil nil ) + ( CapWell net CapWellNet t t t nil nil ) + ( SiBlock net SiBlockNet t t t nil nil ) + ( HR net HRnet t t t nil nil ) + ( hardFence drawing hardFence t t t t nil ) + ( Active net ActiveNet t t t nil nil ) + ( softFence drawing softFence t t t t nil ) + ( Row label RowLbl t t t t nil ) + ( Group drawing Group t t t t nil ) + ( Group label GroupLbl t t t t nil ) + ( Cannotoccupy drawing Cannotoccupy t t t t nil ) + ( Cannotoccupy boundary CannotoccupyBnd t t t t nil ) + ( Canplace drawing Canplace t t t t nil ) + ( ActX net ActXNet t t t nil nil ) + ( A2 drawing A2 t t t t nil ) + ( A1 drawing A1 t t t t nil ) + ( comment drawing comment t t t t nil ) + ( border drawing border t t t t nil ) + ( Pselect net PselectNet t t t nil nil ) + ( Nselect net NselectNet t t t nil nil ) + ( wire drawing wire t t t t nil ) + ( Poly1 net Poly1Net t t t nil nil ) + ( wire label wireLbl t t t t nil ) + ( P1Con net P1ConNet t t t nil nil ) + ( wire flight wireFlt t t t t nil ) + ( Metal1 net Metal1Net t t t nil nil ) + ( device annotate deviceAnt t t t t nil ) + ( Metal2 net Metal2Net t t t nil nil ) + ( Metal3 net Metal3Net t t t nil nil ) + ( device label deviceLbl t t t t nil ) + ( Via net ViaNet t t t nil nil ) + ( Via2 net Via2Net t t t nil nil ) + ( pin label pinLbl t t t t nil ) + ( text drawing text t t t t t ) + ( pin drawing pin t t t t nil ) + ( text drawing1 text1 t t t t nil ) + ( pin annotate pinAnt t t t t nil ) + ( device drawing device t t t t nil ) + ( axis drawing axis t t t t nil ) + ( edgeLayer drawing edgeLayer t t nil t nil ) + ( edgeLayer pin edgeLayerPin t t nil t nil ) + ( snap drawing snap t t nil t nil ) + ( stretch drawing stretch t t nil t nil ) + ( y0 drawing y0 t t nil t nil ) + ( y1 drawing y1 t t nil t nil ) + ( y2 drawing y2 t t nil t nil ) + ( y3 drawing y3 t t nil t nil ) + ( y4 drawing y4 t t nil t nil ) + ( y5 drawing y5 t t nil t nil ) + ( y6 drawing y6 t t nil t nil ) + ( y7 drawing y7 t t nil t nil ) + ( y8 drawing y8 t t nil t nil ) + ( y9 drawing y9 t t nil t nil ) + ( hilite drawing hilite t t nil t nil ) + ( hilite drawing1 hilite1 t t t t nil ) + ( hilite drawing2 hilite2 t t nil t nil ) + ( hilite drawing3 hilite3 t t t t nil ) + ( hilite drawing4 hilite4 t t t t nil ) + ( hilite drawing5 hilite5 t t t t nil ) + ( hilite drawing6 hilite6 t t t t nil ) + ( hilite drawing7 hilite7 t t t t nil ) + ( hilite drawing8 hilite8 t t t t nil ) + ( hilite drawing9 hilite9 t t t t nil ) + ( select drawing select t t nil t nil ) + ( drive drawing drive t t t t nil ) + ( hiz drawing hiz t t t t nil ) + ( resist drawing resist t t t t nil ) + ( spike drawing spike t t t t nil ) + ( supply drawing supply t t t t nil ) + ( unknown drawing unknown t t t t nil ) + ( unset drawing unset t t t t nil ) + ( designFlow drawing designFlow t t t nil nil ) + ( designFlow drawing1 designFlow1 t t t nil nil ) + ( designFlow drawing2 designFlow2 t t t nil nil ) + ( designFlow drawing3 designFlow3 t t t nil nil ) + ( designFlow drawing4 designFlow4 t t t nil nil ) + ( designFlow drawing5 designFlow5 t t t nil nil ) + ( designFlow drawing6 designFlow6 t t t nil nil ) + ( designFlow drawing7 designFlow7 t t t nil nil ) + ( designFlow drawing8 designFlow8 t t t nil nil ) + ( designFlow drawing9 designFlow9 t t t nil nil ) + ( changedLayer tool0 changedLayerTl0 nil nil nil nil nil ) + ( changedLayer tool1 changedLayerTl1 nil nil t nil nil ) + ( marker warning markerWarn t t t t nil ) + ( marker error markerErr t t t t nil ) + ( device drawing1 device1 t t t t nil ) + ( Poly2 net Poly2Net t t t nil nil ) + ( Poly2 drawing Poly2 t t t t t ) + ( P2Con net P2ConNet t t t nil nil ) + ( P2Con drawing P2Con t t t t t ) + ( Pbase net PbaseNet t t t nil nil ) + ( Pbase drawing Pbase t t t t t ) + ( Resistor net ResistorNet t t t nil nil ) + ( Resistor drawing Resistor t t t t t ) + ( Capacitor net CapacitorNet t t t nil nil ) + ( Capacitor drawing Capacitor t t t t t ) + ( Diode net DiodeNet t t t nil nil ) + ( Diode drawing Diode t t t t t ) + ( device drawing2 device2 t t t t nil ) + ( Unrouted drawing Unrouted t t t t nil ) + ( text drawing2 text2 t t t t nil ) + ( Unrouted drawing1 Unrouted1 t t t t nil ) + ( Unrouted drawing2 Unrouted2 t t t t nil ) + ( Unrouted drawing3 Unrouted3 t t t t nil ) + ( Unrouted drawing4 Unrouted4 t t t t nil ) + ( Unrouted drawing5 Unrouted5 t t t t nil ) + ( Unrouted drawing6 Unrouted6 t t t t nil ) + ( Unrouted drawing7 Unrouted7 t t t t nil ) + ( Unrouted drawing8 Unrouted8 t t t t nil ) + ( Unrouted drawing9 Unrouted9 t t t t nil ) + ) ;techDisplays + +; I don't think the following is necessary (or used!) +techLayerProperties( +;( PropName Layer1 [ Layer2 ] PropValue ) + ( contactLimit P2Con 10000 ) + ( eqPinLimit P2Con 10000 ) + ( horizontalJogLength P2Con 2147483648.000000 ) + ( routingGrid P2Con 1.000000 ) + ( verticalJogLength P2Con 2147483648.000000 ) + ( routingGrid Poly2 1.000000 ) + ( contactLimit Active 10000 ) + ( eqPinLimit Active 10000 ) + ( horizontalJogLength Active 2147483648.000000 ) + ( routingGrid Active 1.000000 ) + ( verticalJogLength Active 2147483648.000000 ) + ( routingGrid Poly1 1.000000 ) + ( contactLimit P1Con 10000 ) + ( eqPinLimit P1Con 10000 ) + ( horizontalJogLength P1Con 2147483648.000000 ) + ( routingGrid P1Con 1.000000 ) + ( verticalJogLength P1Con 2147483648.000000 ) + ( contactLimit ActX 10000 ) + ( eqPinLimit ActX 10000 ) + ( horizontalJogLength ActX 2147483648.000000 ) + ( routingGrid ActX 1.000000 ) + ( verticalJogLength ActX 2147483648.000000 ) + ( routingGrid Metal1 1.000000 ) + ( contactLimit Via 10000 ) + ( eqPinLimit Via 10000 ) + ( horizontalJogLength Via 2147483648.000000 ) + ( routingGrid Via 1.000000 ) + ( verticalJogLength Via 2147483648.000000 ) + ( routingGrid Metal2 1.000000 ) +) + +) ;layerDefinitions + + +;******************************** +; DEVICE RULES +;******************************** + +devices( + tcCreateCDSDeviceClass() + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA Via drawing + + ; layer1 purpose1 [implant1] + Metal1 drawing + + ; layer2 purpose2 [implant2] + Metal2 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 1 _NA_) + ) ;symContactDevice + + symContactDevice( + ;( deviceName viaLayer viaPurpose + ( VIA2 Via2 drawing + + ; layer1 purpose1 [implant1] + Metal2 drawing + + ; layer2 purpose2 [implant2] + Metal3 drawing + + ; width length [( row column xPitch yPitch xBias yBias )] + ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) + 2 2 + + ; encLayer1 encLayer2 legalRegion ) + 1 2 _NA_) + ) ;symContactDevice + +) ;devices + + +;******************************** +; LAYER RULES +;******************************** + +layerRules( + streamLayers( + ;( layer streamNumber dataType translate ) + ;( ----- ------------ -------- --------- ) + ( ("background" "drawing") 0 0 nil ) + ( ("grid" "drawing") 0 0 nil ) + ( ("grid" "drawing1") 0 0 nil ) + ( ("Nwell" "drawing") 42 0 t ) + ( ("Pwell" "drawing") 41 0 t ) + ( ("Active" "drawing") 43 0 t ) + ( ("ActX" "drawing") 48 0 t ) + ( ("Pselect" "drawing") 44 0 t ) + ( ("Nselect" "drawing") 45 0 t ) + ( ("Poly1" "drawing") 46 0 t ) + ( ("P1Con" "drawing") 47 0 t ) + ( ("Metal1" "drawing") 49 0 t ) + ( ("Metal2" "drawing") 51 0 t ) + ( ("annotate" "drawing") 0 0 nil ) + ( ("annotate" "drawing1") 0 0 nil ) + ( ("annotate" "drawing2") 0 0 nil ) + ( ("annotate" "drawing3") 0 0 nil ) + ( ("annotate" "drawing4") 0 0 nil ) + ( ("annotate" "drawing5") 0 0 nil ) + ( ("annotate" "drawing6") 0 0 nil ) + ( ("annotate" "drawing7") 0 0 nil ) + ( ("annotate" "drawing8") 0 0 nil ) + ( ("annotate" "drawing9") 0 0 nil ) + ( ("Via" "drawing") 50 0 t ) + ( ("Glass" "drawing") 52 0 t ) + ( ("XP" "drawing") 60 0 t ) + ( ("Metal2" "pin") 0 0 nil ) + ( ("Poly1" "pin") 0 0 nil ) + ( ("prBoundary" "drawing") 0 0 nil ) + ( ("Metal1" "pin") 0 0 nil ) + ( ("prBoundary" "boundary") 0 0 nil ) + ( ("instance" "drawing") 246 0 nil ) + ( ("instance" "label") 0 0 nil ) + ( ("Nwell" "net") 0 0 nil ) + ( ("align" "drawing") 0 0 nil ) + ( ("Pwell" "net") 0 0 nil ) + ( ("hardFence" "drawing") 0 0 nil ) + ( ("Active" "net") 0 0 nil ) + ( ("softFence" "drawing") 0 0 nil ) + ( ("ActX" "net") 0 0 nil ) + ( ("A2" "drawing") 5 0 nil ) + ( ("A1" "drawing") 2 0 nil ) + ( ("comment" "drawing") 0 0 nil ) + ( ("border" "drawing") 0 0 nil ) + ( ("Pselect" "net") 0 0 nil ) + ( ("Nselect" "net") 0 0 nil ) + ( ("wire" "drawing") 0 0 nil ) + ( ("Poly1" "net") 0 0 nil ) + ( ("P1Con" "net") 0 0 nil ) + ( ("Metal1" "net") 0 0 nil ) + ( ("Metal2" "net") 0 0 nil ) + ( ("device" "label") 0 0 nil ) + ( ("Via" "net") 0 0 nil ) + ( ("pin" "label") 0 0 nil ) + ( ("text" "drawing") 63 0 t ) + ( ("pin" "drawing") 0 0 nil ) + ( ("device" "drawing") 0 0 nil ) + ( ("axis" "drawing") 0 0 nil ) + ( ("edgeLayer" "drawing") 0 0 nil ) + ( ("edgeLayer" "pin") 0 0 nil ) + ( ("snap" "drawing") 0 0 nil ) + ( ("stretch" "drawing") 0 0 nil ) + ( ("y0" "drawing") 0 0 nil ) + ( ("y1" "drawing") 0 0 nil ) + ( ("y2" "drawing") 0 0 nil ) + ( ("y3" "drawing") 0 0 nil ) + ( ("y4" "drawing") 0 0 nil ) + ( ("y5" "drawing") 0 0 nil ) + ( ("y6" "drawing") 0 0 nil ) + ( ("y7" "drawing") 0 0 nil ) + ( ("y8" "drawing") 0 0 nil ) + ( ("y9" "drawing") 0 0 nil ) + ( ("hilite" "drawing") 0 0 nil ) + ( ("hilite" "drawing2") 0 0 nil ) + ( ("select" "drawing") 0 0 nil ) + ( ("drive" "drawing") 0 0 nil ) + ( ("hiz" "drawing") 0 0 nil ) + ( ("resist" "drawing") 0 0 nil ) + ( ("spike" "drawing") 0 0 nil ) + ( ("supply" "drawing") 0 0 nil ) + ( ("unknown" "drawing") 0 0 nil ) + ( ("unset" "drawing") 0 0 nil ) + ( ("changedLayer" "tool0") 0 0 nil ) + ( ("Resistor" "net") 0 0 nil ) + ( ("Resistor" "drawing") 0 0 nil ) + ( ("Capacitor" "net") 0 0 nil ) + ( ("Capacitor" "drawing") 0 0 nil ) + ( ("Diode" "net") 0 0 nil ) + ( ("Diode" "drawing") 0 0 nil ) + ( ("Poly2" "net") 0 0 nil ) + ( ("Poly2" "drawing") 0 0 nil ) + ( ("P2Con" "net") 0 0 nil ) + ( ("P2Con" "drawing") 0 0 nil ) + ( ("Pbase" "drawing") 0 0 nil ) + ( ("Pbase" "net") 0 0 nil ) + ( P2Con 0 0 nil ) + ( Poly2 0 0 nil ) + ( Pwell 0 0 nil ) + ( Nwell 0 0 nil ) + ( Active 0 0 nil ) + ( Pselect 0 0 nil ) + ( Nselect 0 0 nil ) + ( Poly1 0 0 nil ) + ( P1Con 0 0 nil ) + ( ActX 0 0 nil ) + ( Metal1 0 0 nil ) + ( Via 0 0 nil ) + ( Metal2 0 0 nil ) + ( Glass 0 0 nil ) + ( XP 0 0 nil ) + ( ("Via2" "drawing") 50 0 t ) + ( ("Via2" "net") 0 0 nil ) + ( ("Metal3" "drawing") 50 0 t ) + ( ("Metal3" "net") 0 0 nil ) + ( ("Metal3" "pin") 0 0 nil ) + ( ("CapWell" "drawing") 0 0 nil ) + ( ("CapWell" "net") 0 0 nil ) + ( ("SiBlock" "drawing") 0 0 nil ) + ( ("SiBlock" "net") 0 0 nil ) + ( ("HR" "drawing") 0 0 nil ) + ( ("HR" "net") 0 0 nil ) + ) ;streamLayers + + viaLayers( + ;( layer1 viaLayer layer2 ) + ;( ------ -------- ------ ) + ( Metal2 Via2 Metal3 ) + ( Metal1 Via Metal2 ) + ( Active ActX Poly1 ) + ( Poly1 P1Con Metal1 ) + ( Poly2 P2Con Metal1 ) + ) ;viaLayers + +) ;layerRules + + +;******************************** +; PHYSICAL RULES +;******************************** + +physicalRules( + orderedSpacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minEnclosure "prBoundary" "Metal1" 0.0 ) + ( minEnclosure "Metal2" "Via" 1.0 ) + ( minEnclosure "Metal1" "Via" 1.0 ) + ( minEnclosure "Metal1" "P1Con" 1.0 ) + ( minEnclosure "Metal1" "ActX" 1.0 ) + ( minEnclosure "Nselect" "Active" 2.0 ) + ( minEnclosure "Pselect" "Active" 2.0 ) + ( minEnclosure "Active" "ActX" 1.0 ) + ( minEnclosure "Pwell" "Active" 5.0 ) + ( minEnclosure "Nwell" "Active" 5.0 ) + ) ;orderedSpacingRules + + spacingRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( minSpacing "P2Con" 2.0 ) + ( minSpacing "Poly2" 3.0 ) + ( minSpacing "Pwell" 9.0 ) + ( minSpacing "Nwell" 9.0 ) + ( minSpacing "Active" 3.0 ) + ( minSpacing "Pselect" 2.0 ) + ( minSpacing "Nselect" 2.0 ) + ( minSpacing "Poly1" 2.0 ) + ( minSpacing "P1Con" 2.0 ) + ( minSpacing "ActX" 2.0 ) + ( minSpacing "Metal1" 3.0 ) + ( minSpacing "Via" 3.0 ) + ( minSpacing "Via2" 3.0 ) + ( minSpacing "Metal2" 3.0 ) + ( minSpacing "Metal3" 4.0 ) + ( minSpacing "Glass" 75.0 ) + ( minSpacing "XP" 100.0 ) + ( minSpacing "Metal2" 4.0 ) + ( minSpacing "P1Con" "Via" 2.0 ) + ( minSpacing "ActX" "Via" 2.0 ) + ( minSpacing "ActX" "P2Con" 2.0 ) + ( minSpacing "Poly2" "P2Con" 4.0 ) + ( minSpacing "Poly1" "P1Con" 4.0 ) + ( minSpacing "ActX" "P1Con" 2.0 ) + ( minSpacing "Active" "P1Con" 2.0 ) + ( minSpacing "Active" "Poly2" 2.0 ) + ( minSpacing "Poly1" "Poly2" 2.0 ) + ( minSpacing "Active" "Poly1" 2.0 ) + ( minSpacing "ActX" "Poly1" 2.0 ) + ( minSpacing "Pselect" "Nselect" 0.0 ) + ( minSpacing "Nwell" "Pwell" 9.0 ) + ( minWidth "P2Con" 2.0 ) + ( minWidth "Poly2" 3.0 ) + ( minWidth "Pwell" 10.0 ) + ( minWidth "Nwell" 10.0 ) + ( minWidth "Active" 3.0 ) + ( minWidth "Pselect" 2.0 ) + ( minWidth "Nselect" 2.0 ) + ( minWidth "Poly1" 2.0 ) + ( minWidth "P1Con" 2.0 ) + ( minWidth "ActX" 2.0 ) + ( minWidth "Metal1" 4.0 ) + ( minWidth "Via" 2.0 ) + ( minWidth "Metal2" 4.0 ) + ( minWidth "Glass" 75.0 ) + ( minWidth "XP" 100.0 ) + ( minWidth "Metal3" 6.0 ) + ) ;spacingRules + + mfgGridResolution( + ( 1.000000 ) + ) ;mfgGridResolution + +) ;physicalRules + + +;******************************** +; ELECTRICAL RULES +;******************************** + +electricalRules( + characterizationRules( + ;( rule layer1 layer2 value ) + ;( ---- ------ ------ ----- ) + ( areaCap "P2Con" 0.0 ) + ( areaCap "Poly2" 0.0 ) + ( areaCap "Active" 0.0 ) + ( areaCap "Poly1" 6e-05 ) + ( areaCap "P1Con" 0.0 ) + ( areaCap "ActX" 0.0 ) + ( areaCap "Metal1" 2.6e-05 ) + ( areaCap "Via" 0.0 ) + ( areaCap "Metal2" 1.6e-05 ) + ( edgeCapacitance "P2Con" 0.0 ) + ( edgeCapacitance "Poly2" 0.0 ) + ( edgeCapacitance "Active" 0.0 ) + ( edgeCapacitance "Poly1" 0.0 ) + ( edgeCapacitance "P1Con" 0.0 ) + ( edgeCapacitance "ActX" 0.0 ) + ( edgeCapacitance "Metal1" 0.0 ) + ( edgeCapacitance "Via" 0.0 ) + ( edgeCapacitance "Metal2" 0.0 ) + ( sheetRes "P2Con" 0.0 ) + ( sheetRes "Poly2" 0.0 ) + ( sheetRes "Active" 0.0 ) + ( sheetRes "Poly1" 23.0 ) + ( sheetRes "P1Con" 0.0 ) + ( sheetRes "ActX" 0.0 ) + ( sheetRes "Metal1" 0.04 ) + ( sheetRes "Via" 0.0 ) + ( sheetRes "Metal2" 0.07 ) + ( currentDensity "P2Con" 1.0 ) + ( currentDensity "Poly2" 1.0 ) + ( currentDensity "Active" 1.0 ) + ( currentDensity "Poly1" 1.0 ) + ( currentDensity "P1Con" 1.0 ) + ( currentDensity "ActX" 1.0 ) + ( currentDensity "Metal1" 1.0 ) + ( currentDensity "Via" 1.0 ) + ( currentDensity "Metal2" 1.0 ) + ) ;characterizationRules + +) ;electricalRules + + +;******************************** +; LAYOUT EDITOR RULES +;******************************** +; specifies the ordering of the layers in the LSW + +leRules( + leLswLayers( + ;( layer purpose ) + ; ----- ------- ) + ( Nwell drawing ) + ( Pselect drawing ) + ( Nselect drawing ) + ( Active drawing ) + ( ActX drawing ) + ( Poly1 drawing ) + ( P1Con drawing ) + ( Metal1 drawing ) + ( Via drawing ) + ( Metal2 drawing ) + ( Via2 drawing ) + ( Metal3 drawing ) + ( Poly1 pin ) + ( Metal1 pin ) + ( Metal2 pin ) + ( Metal3 pin ) + ( Poly2 drawing ) + ( P2Con drawing ) + ( instance drawing ) + ( text drawing ) + ( CapWell drawing ) + ( SiBlock drawing ) + ( HR drawing ) + ( Pbase drawing ) + ( Resistor drawing ) + ( Capacitor drawing ) + ( Diode drawing ) + ( Glass drawing ) + ( XP drawing ) + + ) ;leLswLayers +) ;leRules + + +;******************************** +; VIRTUOSO XL RULES +;******************************** +; specifies the ordering of the layers in the LSW + +lxRules( + lxExtractLayers( + (Metal1 Metal2 Metal3) + ) ;lxExtractLayers +) ;lxRules + diff --git a/technology/setup_scripts/setup_openram_scn4m_subm.py b/technology/setup_scripts/setup_openram_scn4m_subm.py new file mode 100644 index 00000000..19a4960c --- /dev/null +++ b/technology/setup_scripts/setup_openram_scn4m_subm.py @@ -0,0 +1,41 @@ +#!/usr/bin/python +""" +This type of setup script should be placed in the setup_scripts directory in the trunk +""" + +import sys +import os + +TECHNOLOGY = "scn4m_subm" + + +########################## +# CDK paths + +# os.environ["CDK_DIR"] = CDK_DIR #PDK path +# os.environ["SYSTEM_CDS_LIB_DIR"] = "{0}/cdssetup".format(CDK_DIR) +# os.environ["CDS_SITE"] = CDK_DIR +os.environ["MGC_TMPDIR"] = "/tmp" + +########################### +# OpenRAM Paths + + +try: + DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME")) +except: + OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) + DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech" +os.environ["DRCLVS_HOME"] = DRCLVS_HOME + +# try: +# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) +# except: +OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) +os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) + +########################## +# Paths required for OPENRAM to function + +LOCAL = "{0}/..".format(os.path.dirname(__file__)) +sys.path.append("{0}/{1}/tech".format(LOCAL,TECHNOLOGY))