diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py
index 43c8b044..cf9ac8cd 100644
--- a/compiler/modules/control_logic_delay.py
+++ b/compiler/modules/control_logic_delay.py
@@ -573,7 +573,7 @@ class control_logic_delay(design.design):
         out_pos = out_pin.center()
         in_pin = self.wl_en_driver_inst.get_pin("A")
         in_pos = in_pin.center()
-        mid1 = vector(in_pos.x, out_pos.y)
+        mid1 = vector(out_pos.x, in_pos.y)
         self.add_path(out_pin.layer, [out_pos, mid1, in_pos])
         self.add_via_stack_center(from_layer=out_pin.layer,
                                   to_layer=in_pin.layer,
diff --git a/compiler/modules/multi_delay_chain.py b/compiler/modules/multi_delay_chain.py
index 340afcd6..81735448 100644
--- a/compiler/modules/multi_delay_chain.py
+++ b/compiler/modules/multi_delay_chain.py
@@ -206,7 +206,7 @@ class multi_delay_chain(design.design):
         # It gets routed down a bit to prevent overlapping adjacent
         # M3 when connecting to vertical bus
         a_pin = self.driver_inst_list[0].get_pin("A")
-        mid_loc = vector(a_pin.cx(), a_pin.cy() - self.m3_pitch) # Not 100% sure correct
+        mid_loc = vector(a_pin.cx(), a_pin.cy() - self.m3_pitch)
         self.add_via_stack_center(from_layer=a_pin.layer,
                                         to_layer="m3",
                                         offset=mid_loc)