Many edits.

Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
This commit is contained in:
mrg
2020-11-22 08:24:47 -08:00
parent 6e51c3cda0
commit 5ee3f4cc66
6 changed files with 61 additions and 49 deletions
+6 -11
View File
@@ -35,11 +35,6 @@ class bitcell_base_array(design.design):
self.rbl_wordline_names = [[] for port in self.all_ports]
self.all_rbl_wordline_names = []
# The supply pin names
self.bitcell_supplies = self.cell.supplies
# If the technology needs renaming of the supplies
self.supplies = ["vdd", "gnd"]
def create_all_bitline_names(self):
for col in range(self.column_size):
for port in self.all_ports:
@@ -63,8 +58,8 @@ class bitcell_base_array(design.design):
self.add_pin(bl_name, "INOUT")
for wl_name in self.get_wordline_names():
self.add_pin(wl_name, "INPUT")
self.add_pin(self.supplies[0], "POWER")
self.add_pin(self.supplies[1], "GROUND")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def get_bitcell_pins(self, row, col):
"""
@@ -75,8 +70,8 @@ class bitcell_base_array(design.design):
for port in self.all_ports:
bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
bitcell_pins.append(self.bitcell_supplies[0])
bitcell_pins.append(self.bitcell_supplies[1])
bitcell_pins.append("vdd")
bitcell_pins.append("gnd")
return bitcell_pins
@@ -166,8 +161,8 @@ class bitcell_base_array(design.design):
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
for (pin_name, new_name) in zip(self.bitcell_supplies, self.supplies):
self.copy_layout_pin(inst, pin_name, new_name)
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
def _adjust_x_offset(self, xoffset, col, col_offset):
tempx = xoffset