luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-03 16:31:08 +02:00
Code Issues Packages Projects Releases Wiki Activity

Many edits.

Browse Source 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
This commit is contained in:
mrg
2020-11-22 08:24:47 -08:00
parent 6e51c3cda0
commit 5ee3f4cc66
6 changed files with 61 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/base/custom_cell_properties.py
+15 -1
View File
@@ -208,12 +208,18 @@ class cell_properties():
self._bitcell_2port = _bitcell(["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"],
["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"])
self._col_cap_1port = _bitcell(["bl", "br", "vdd"],
["OUTPUT", "OUTPUT", "POWER"])
self._row_cap_1port = _bitcell(["wl", "gnd"],
["INPUT", "POWER", "GROUND"])
self._col_cap_2port = _bitcell(["bl0", "br0", "bl1", "br1", "vdd"],
["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "POWER"])
self._row_cap_2port = _bitcell(["wl0", "wl1", "gnd"],
["INPUT", "INPUT", "POWER", "GROUND"])
@property
def ptx(self):
return self._ptx
@@ -258,6 +264,14 @@ class cell_properties():
def bitcell_2port(self):
return self._bitcell_2port
@property
def col_cap_1port(self):
return self._col_cap_1port
@property
def row_cap_1port(self):
return self._row_cap_1port
@property
def col_cap_2port(self):
return self._col_cap_2port
compiler/base/hierarchy_spice.py
+1 -1
View File
@@ -48,7 +48,7 @@ class spice():
else:
self.lvs_file = self.sp_file
self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "BIAS", "POWER", "GROUND"]
# Holds subckts/mods for this module
self.mods = []
# Holds the pins for this module (in order)