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try it without pre_sen

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samuelkcrow
2022-07-21 19:35:01 -07:00
parent 71f241f660
commit 5edb511dab
1 changed files with 1 additions and 1 deletions
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compiler/modules/control_logic_delay.py
+1 -1
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@@ -631,7 +631,7 @@ class control_logic_delay(design.design):
# GATE FOR S_EN
self.s_en_gate_inst = self.add_inst(name="and_s_en",
mod=self.sen_and3)
self.connect_inst(["pre_sen", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
self.connect_inst(["glitch3_bar", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
def place_sen_row(self, row):
x_offset = self.control_x_offset