luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity

Force vertical vias on pnand3

Browse Source
This commit is contained in:
mrg
2020-02-06 16:44:19 +00:00
parent f0ecf385e8
commit 5e514215d5
1 changed files with 6 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/pgates/pnand3.py
+6 -3
View File
@@ -233,11 +233,14 @@ class pnand3(pgate.pgate):
# Go up to metal2 for ease on all output pins
self.add_via_center(layers=self.m1_stack,
offset=pmos1_pin.center())
offset=pmos1_pin.center(),
directions=("V", "V"))
self.add_via_center(layers=self.m1_stack,
offset=pmos3_pin.center())
offset=pmos3_pin.center(),
directions=("V", "V"))
self.add_via_center(layers=self.m1_stack,
offset=nmos3_pin.center())
offset=nmos3_pin.center(),
directions=("V", "V"))
# PMOS3 and NMOS3 are drain aligned
self.add_path("m2", [pmos3_pin.center(), nmos3_pin.uc()])