luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

remove whitespace

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2023-08-03 00:42:42 -07:00
parent 61cfa55d75
commit 5e01bad2ee
4 changed files with 26 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/dummy_array.py
+3 -3
View File
@@ -6,7 +6,7 @@
from openram.sram_factory import factory
from openram import OPTS
from .bitcell_base_array import bitcell_base_array
from openram.base import geometry
from openram.base import geometry
from .pattern import pattern
class dummy_array(bitcell_base_array):
@@ -53,8 +53,8 @@ class dummy_array(bitcell_base_array):
""" Create the module instances used in this design """
self.cell_inst={}
core_block = [[0 for x in range(1)] for y in range(2)]
core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
core_block[0][(0+self.mirror) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
core_block[0][(1+self.mirror) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size)