Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

compiler/example_configs/big_config_scn4m_subm.py

@@ -0,0 +1,14 @@
+word_size = 8
+num_words = 128
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [ 5.0 ]
+temperatures = [ 25 ]
+
+output_path = "temp"
+output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/example_config_1rw_1r_scn4m_subm.py

@@ -0,0 +1,20 @@
+word_size = 2
+num_words = 16
+
+bitcell = "bitcell_1rw_1r"
+replica_bitcell = "replica_bitcell_1rw_1r"
+num_rw_ports = 1
+num_r_ports = 1
+num_w_ports = 0
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+output_path = "temp"
+output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/example_config_freepdk45.py

@@ -0,0 +1,11 @@
+word_size = 2
+num_words = 16
+
+tech_name = "freepdk45"
+process_corners = ["TT"]
+supply_voltages = [1.0]
+temperatures = [25]
+
+output_path = "temp"
+output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+

compiler/example_configs/example_config_scn4m_subm.py

@@ -0,0 +1,14 @@
+word_size = 2
+num_words = 16
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+output_path = "temp"
+output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

compiler/example_configs/medium_config_scn4m_subm.py

@@ -0,0 +1,14 @@
+word_size = 16
+num_words = 256
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [ 3.3 ]
+temperatures = [ 25 ]
+
+output_path = "temp"
+output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"