mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed pruned golden lib file from error in last commit.
This commit is contained in:
Hunter Nichols
parent
da1b003d10
commit
5c8a00ea1d
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@ -1,4 +1,4 @@
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library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
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delay_model : "table_lookup";
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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voltage_unit : "1v" ;
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@ -9,7 +9,7 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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pulling_resistance_unit :"1kohm" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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operating_conditions(OC){
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process : 1.0 ;
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process : 1.0 ;
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voltage : 1.0 ;
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voltage : 5.0 ;
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temperature : 25;
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temperature : 25;
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}
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}
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@ -22,7 +22,7 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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slew_lower_threshold_pct_rise : 10.0 ;
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slew_lower_threshold_pct_rise : 10.0 ;
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slew_upper_threshold_pct_rise : 90.0 ;
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slew_upper_threshold_pct_rise : 90.0 ;
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nom_voltage : 1.0;
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nom_voltage : 5.0;
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nom_temperature : 25;
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nom_temperature : 25;
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nom_process : 1.0;
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nom_process : 1.0;
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default_cell_leakage_power : 0.0 ;
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default_cell_leakage_power : 0.0 ;
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@ -38,15 +38,15 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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lu_table_template(CELL_TABLE){
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lu_table_template(CELL_TABLE){
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variable_1 : input_net_transition;
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variable_1 : input_net_transition;
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variable_2 : total_output_net_capacitance;
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variable_2 : total_output_net_capacitance;
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index_1("0.00125, 0.005, 0.04");
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index_1("0.0125, 0.05, 0.4");
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index_2("0.052275, 0.2091, 1.6728");
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index_2("2.45605, 9.8242, 78.5936");
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}
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}
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lu_table_template(CONSTRAINT_TABLE){
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lu_table_template(CONSTRAINT_TABLE){
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variable_1 : related_pin_transition;
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variable_1 : related_pin_transition;
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variable_2 : constrained_pin_transition;
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variable_2 : constrained_pin_transition;
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index_1("0.00125, 0.005, 0.04");
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index_1("0.0125, 0.05, 0.4");
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index_2("0.00125, 0.005, 0.04");
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index_2("0.0125, 0.05, 0.4");
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}
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}
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default_operating_conditions : OC;
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default_operating_conditions : OC;
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@ -68,7 +68,7 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
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bit_to : 3;
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bit_to : 3;
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}
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}
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cell (sram_2_16_1_freepdk45){
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cell (sram_2_16_1_scn4m_subm){
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memory(){
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memory(){
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type : ram;
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type : ram;
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address_width : 4;
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address_width : 4;
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@ -78,17 +78,17 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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dont_use : true;
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map_only : true;
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map_only : true;
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dont_touch : true;
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dont_touch : true;
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area : 977.4951374999999;
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area : 60774.3;
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leakage_power () {
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leakage_power () {
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when : "CSb0";
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when : "CSb0";
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value : 0.0011164579999999999;
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value : 0.0009813788999999999;
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}
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}
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cell_leakage_power : 0;
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cell_leakage_power : 0;
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bus(DIN0){
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bus(DIN0){
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bus_type : DATA;
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bus_type : DATA;
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direction : input;
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direction : input;
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capacitance : 0.2091;
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capacitance : 9.8242;
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memory_write(){
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memory_write(){
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address : ADDR0;
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address : ADDR0;
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clocked_on : clk0;
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clocked_on : clk0;
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@ -98,28 +98,28 @@ cell (sram_2_16_1_freepdk45){
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timing_type : setup_rising;
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timing_type : setup_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.033, 0.033, 0.039",\
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values("0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039",\
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"0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039");
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"0.167, 0.167, 0.228");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.027, 0.027, 0.033",\
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values("0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033",\
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"0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033");
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"0.131, 0.125, 0.137");
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}
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}
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}
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}
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timing(){
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timing(){
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timing_type : hold_rising;
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timing_type : hold_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("-0.01, -0.016, -0.022",\
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values("-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022",\
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"-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022");
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"-0.065, -0.071, -0.114");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.016, -0.016, -0.016",\
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values("-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016",\
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"-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016");
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"-0.089, -0.089, -0.089");
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}
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}
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}
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}
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}
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}
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@ -127,8 +127,8 @@ cell (sram_2_16_1_freepdk45){
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bus(DOUT0){
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bus(DOUT0){
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bus_type : DATA;
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bus_type : DATA;
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direction : output;
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direction : output;
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max_capacitance : 1.6728;
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max_capacitance : 78.5936;
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min_capacitance : 0.052275;
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min_capacitance : 2.45605;
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memory_read(){
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memory_read(){
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address : ADDR0;
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address : ADDR0;
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}
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}
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@ -138,24 +138,24 @@ cell (sram_2_16_1_freepdk45){
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related_pin : "clk0";
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related_pin : "clk0";
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timing_type : rising_edge;
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timing_type : rising_edge;
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cell_rise(CELL_TABLE) {
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cell_rise(CELL_TABLE) {
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values("0.235, 0.235, 0.239",\
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values("1.542, 1.562, 1.738",\
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"0.235, 0.236, 0.24",\
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"1.545, 1.565, 1.741",\
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"0.241, 0.242, 0.246");
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"1.609, 1.629, 1.805");
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}
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}
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cell_fall(CELL_TABLE) {
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cell_fall(CELL_TABLE) {
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values("2.583, 2.585, 2.612",\
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values("3.446, 3.505, 3.924",\
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"2.584, 2.585, 2.613",\
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"3.45, 3.508, 3.927",\
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"2.59, 2.592, 2.62");
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"3.491, 3.55, 3.97");
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}
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}
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rise_transition(CELL_TABLE) {
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rise_transition(CELL_TABLE) {
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values("0.022, 0.022, 0.03",\
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values("0.129, 0.169, 0.573",\
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"0.022, 0.023, 0.03",\
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"0.129, 0.169, 0.573",\
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"0.022, 0.022, 0.03");
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"0.129, 0.169, 0.573");
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}
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}
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fall_transition(CELL_TABLE) {
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fall_transition(CELL_TABLE) {
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values("0.078, 0.079, 0.083",\
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values("0.457, 0.481, 0.956",\
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"0.078, 0.079, 0.083",\
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"0.457, 0.481, 0.956",\
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"0.079, 0.079, 0.083");
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"0.459, 0.483, 0.957");
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}
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}
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}
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}
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}
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}
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@ -164,35 +164,35 @@ cell (sram_2_16_1_freepdk45){
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bus(ADDR0){
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bus(ADDR0){
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bus_type : ADDR;
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bus_type : ADDR;
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direction : input;
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direction : input;
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capacitance : 0.2091;
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capacitance : 9.8242;
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max_transition : 0.04;
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max_transition : 0.4;
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pin(ADDR0[3:0]){
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pin(ADDR0[3:0]){
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timing(){
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timing(){
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timing_type : setup_rising;
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timing_type : setup_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.033, 0.033, 0.039",\
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values("0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039",\
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"0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039");
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"0.167, 0.167, 0.228");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.027, 0.027, 0.033",\
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values("0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033",\
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"0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033");
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"0.131, 0.125, 0.137");
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}
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}
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}
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}
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timing(){
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timing(){
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timing_type : hold_rising;
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timing_type : hold_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("-0.01, -0.016, -0.022",\
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values("-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022",\
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"-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022");
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"-0.065, -0.071, -0.114");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.016, -0.016, -0.016",\
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values("-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016",\
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"-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016");
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"-0.089, -0.089, -0.089");
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}
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}
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}
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}
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}
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}
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@ -200,66 +200,66 @@ cell (sram_2_16_1_freepdk45){
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pin(CSb0){
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pin(CSb0){
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direction : input;
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direction : input;
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capacitance : 0.2091;
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capacitance : 9.8242;
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timing(){
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timing(){
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timing_type : setup_rising;
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timing_type : setup_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.033, 0.033, 0.039",\
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values("0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039",\
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"0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039");
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"0.167, 0.167, 0.228");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.027, 0.027, 0.033",\
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values("0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033",\
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"0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033");
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"0.131, 0.125, 0.137");
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}
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}
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}
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}
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timing(){
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timing(){
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timing_type : hold_rising;
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timing_type : hold_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("-0.01, -0.016, -0.022",\
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values("-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022",\
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"-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022");
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"-0.065, -0.071, -0.114");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.016, -0.016, -0.016",\
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values("-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016",\
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"-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016");
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"-0.089, -0.089, -0.089");
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}
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}
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}
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}
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}
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}
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pin(WEb0){
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pin(WEb0){
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direction : input;
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direction : input;
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capacitance : 0.2091;
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capacitance : 9.8242;
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timing(){
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timing(){
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timing_type : setup_rising;
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timing_type : setup_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.033, 0.033, 0.039",\
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values("0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039",\
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"0.167, 0.167, 0.228",\
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"0.033, 0.033, 0.039");
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"0.167, 0.167, 0.228");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.027, 0.027, 0.033",\
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values("0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033",\
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"0.131, 0.125, 0.137",\
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"0.027, 0.027, 0.033");
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"0.131, 0.125, 0.137");
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}
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}
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}
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}
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timing(){
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timing(){
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timing_type : hold_rising;
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timing_type : hold_rising;
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related_pin : "clk0";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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rise_constraint(CONSTRAINT_TABLE) {
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values("-0.01, -0.016, -0.022",\
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values("-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022",\
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"-0.065, -0.071, -0.114",\
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"-0.01, -0.016, -0.022");
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"-0.065, -0.071, -0.114");
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}
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}
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fall_constraint(CONSTRAINT_TABLE) {
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.016, -0.016, -0.016",\
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values("-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016",\
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"-0.089, -0.089, -0.089",\
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"-0.016, -0.016, -0.016");
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"-0.089, -0.089, -0.089");
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}
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}
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}
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}
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}
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}
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@ -267,23 +267,23 @@ cell (sram_2_16_1_freepdk45){
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pin(clk0){
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pin(clk0){
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clock : true;
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clock : true;
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direction : input;
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direction : input;
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capacitance : 0.2091;
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capacitance : 9.8242;
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internal_power(){
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internal_power(){
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when : "!CSb0 & clk0 & !WEb0";
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when : "!CSb0 & clk0 & !WEb0";
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rise_power(scalar){
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rise_power(scalar){
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values("0.03599689694444445");
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values("9.602821763527778");
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}
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}
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fall_power(scalar){
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fall_power(scalar){
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values("0.03599689694444445");
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values("9.602821763527778");
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}
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}
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}
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}
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internal_power(){
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internal_power(){
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when : "!CSb0 & !clk0 & WEb0";
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when : "!CSb0 & !clk0 & WEb0";
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rise_power(scalar){
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rise_power(scalar){
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values("0.029906643888888886");
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values("8.647938152416664");
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}
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}
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fall_power(scalar){
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fall_power(scalar){
|
||||||
values("0.029906643888888886");
|
values("8.647938152416664");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
internal_power(){
|
internal_power(){
|
||||||
|
|
@ -299,20 +299,20 @@ cell (sram_2_16_1_freepdk45){
|
||||||
timing_type :"min_pulse_width";
|
timing_type :"min_pulse_width";
|
||||||
related_pin : clk0;
|
related_pin : clk0;
|
||||||
rise_constraint(scalar) {
|
rise_constraint(scalar) {
|
||||||
values("2.422");
|
values("2.344");
|
||||||
}
|
}
|
||||||
fall_constraint(scalar) {
|
fall_constraint(scalar) {
|
||||||
values("2.422");
|
values("2.344");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
timing(){
|
timing(){
|
||||||
timing_type :"minimum_period";
|
timing_type :"minimum_period";
|
||||||
related_pin : clk0;
|
related_pin : clk0;
|
||||||
rise_constraint(scalar) {
|
rise_constraint(scalar) {
|
||||||
values("4.844");
|
values("4.688");
|
||||||
}
|
}
|
||||||
fall_constraint(scalar) {
|
fall_constraint(scalar) {
|
||||||
values("4.844");
|
values("4.688");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue