From 5c4ee911aaae8e34641a7706d3107848fb890429 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 11 Nov 2018 07:22:13 -0800 Subject: [PATCH] added another VLSI logo and fixed control port numbering --- compiler/characterizer/lib.py | 4 ++-- compiler/datasheet/datasheet.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 3909f202..da96894d 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -569,7 +569,7 @@ class lib: for port in self.all_ports: #CSb timings datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( - "CSb{1}[{0}:0]".format(self.sram.word_size - 1, port), + "CSb{0}".format(port), min(list(map(round_time,self.times["setup_times_LH"]))), max(list(map(round_time,self.times["setup_times_LH"]))), @@ -608,7 +608,7 @@ class lib: #WEb timings datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format( - "WEb{1}[{0}:0]".format(self.sram.word_size - 1, port), + "WEb{0}".format(port), min(list(map(round_time,self.times["setup_times_LH"]))), max(list(map(round_time,self.times["setup_times_LH"]))), diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index 144f1968..70957b75 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -41,7 +41,7 @@ class datasheet(): LVS = 'skipped' PEX = 'skipped' - + self.html +='VLSIDA' self.html +='

'+ self.name + '.html' + '

' self.html +='

'+ 'DRC: ' + str(DRC) + '

' self.html +='

'+ 'LVS: ' + str(LVS) + '

'