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Fix bug in not adding RBLs in local bitcell array

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This commit is contained in:
mrg
2020-08-18 15:11:10 -07:00
parent 2643a96f97
commit 59d65c46c3
2 changed files with 43 additions and 2 deletions
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compiler/modules/local_bitcell_array.py
+2 -2
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@@ -64,7 +64,8 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
self.bitcell_array = factory.create(module_type="replica_bitcell_array",
cols=self.cols,
rows=self.rows,
rbl=self.rbl)
rbl=self.rbl,
add_rbl=self.add_rbl)
self.add_mod(self.bitcell_array)
self.wl_array = factory.create(module_type="wordline_buffer_array",
@@ -82,7 +83,6 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
self.replica_names = self.bitcell_array.get_rbl_wordline_names()
self.bitline_names = self.bitcell_array.get_inouts()
# Arrays are always:
# word lines (bottom to top)
# bit lines (left to right)