From 59d65c46c3b6b47e95f04903b2135f84492d67c3 Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Tue, 18 Aug 2020 15:11:10 -0700
Subject: [PATCH] Fix bug in not adding RBLs in local bitcell array

---
 compiler/modules/local_bitcell_array.py       |  4 +-
 .../05_local_bitcell_array_1rw_1r_test.py     | 41 +++++++++++++++++++
 2 files changed, 43 insertions(+), 2 deletions(-)
 create mode 100755 compiler/tests/05_local_bitcell_array_1rw_1r_test.py

diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py
index 88cd9c17..413d1915 100644
--- a/compiler/modules/local_bitcell_array.py
+++ b/compiler/modules/local_bitcell_array.py
@@ -64,7 +64,8 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
         self.bitcell_array = factory.create(module_type="replica_bitcell_array",
                                             cols=self.cols,
                                             rows=self.rows,
-                                            rbl=self.rbl)
+                                            rbl=self.rbl,
+                                            add_rbl=self.add_rbl)
         self.add_mod(self.bitcell_array)
 
         self.wl_array = factory.create(module_type="wordline_buffer_array",
@@ -82,7 +83,6 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
         self.replica_names = self.bitcell_array.get_rbl_wordline_names()
 
         self.bitline_names = self.bitcell_array.get_inouts()
-        
         # Arrays are always:
         # word lines (bottom to top)
         # bit lines (left to right)
diff --git a/compiler/tests/05_local_bitcell_array_1rw_1r_test.py b/compiler/tests/05_local_bitcell_array_1rw_1r_test.py
new file mode 100755
index 00000000..9ef92bb2
--- /dev/null
+++ b/compiler/tests/05_local_bitcell_array_1rw_1r_test.py
@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from sram_factory import factory
+import debug
+
+
+#@unittest.skip("SKIPPING 05_local_bitcell_array_test")
+class local_bitcell_array_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica")
+        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[0, 0])
+        self.local_check(a)
+
+        debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
+        a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0])
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())