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Altering certain tests to include multiport checks.
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@@ -24,17 +24,17 @@ class precharge_test(openram_test):
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debug.info(2, "Checking precharge for pbitcell")
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OPTS.bitcell = "pbitcell"
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OPTS.num_rw_ports = 2
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OPTS.num_r_ports = 2
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OPTS.num_w_ports = 2
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(pc)
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pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2")
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pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1")
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self.local_check(pc)
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pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl4", bitcell_br="br4")
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pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2")
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self.local_check(pc)
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globals.end_openram()
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