From 586c72e4f77aeb491e901ec51681384399554347 Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Sun, 9 Sep 2018 22:08:03 -0700 Subject: [PATCH] Altering certain tests to include multiport checks. --- compiler/tests/04_precharge_test.py | 10 +++---- .../tests/04_single_level_column_mux_test.py | 14 ++++++++++ .../07_single_level_column_mux_array_test.py | 26 +++++++++++++++++++ compiler/tests/08_precharge_array_test.py | 10 +++---- compiler/tests/19_psingle_bank_test.py | 21 ++++++++++++++- 5 files changed, 70 insertions(+), 11 deletions(-) mode change 100755 => 100644 compiler/tests/04_single_level_column_mux_test.py mode change 100755 => 100644 compiler/tests/07_single_level_column_mux_array_test.py mode change 100755 => 100644 compiler/tests/19_psingle_bank_test.py diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 3bc44c47..15ed63b5 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -24,16 +24,16 @@ class precharge_test(openram_test): debug.info(2, "Checking precharge for pbitcell") OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 2 - OPTS.num_r_ports = 2 - OPTS.num_w_ports = 2 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl4", bitcell_br="br4") + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py old mode 100755 new mode 100644 index 01dc4445..417c9e83 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -23,6 +23,20 @@ class single_level_column_mux_test(openram_test): debug.info(2, "Checking column mux") tx = single_level_column_mux.single_level_column_mux(tx_size=8) self.local_check(tx) + + debug.info(2, "Checking column mux for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(tx) + + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py old mode 100755 new mode 100644 index ea231292..1a9d33c3 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -27,6 +27,32 @@ class single_level_column_mux_test(openram_test): debug.info(1, "Testing sample for 8-way column_mux_array") a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4) self.local_check(a) + + debug.info(2, "Checking column mux array for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + debug.info(1, "Testing sample for 2-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 4-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 0549cd52..a18478f5 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -24,17 +24,17 @@ class precharge_test(openram_test): debug.info(2, "Checking precharge for pbitcell") OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 2 - OPTS.num_r_ports = 2 - OPTS.num_w_ports = 2 + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") self.local_check(pc) - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1") self.local_check(pc) - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl4", bitcell_br="br4") + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") self.local_check(pc) globals.end_openram() diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py old mode 100755 new mode 100644 index f377a3db..5ff00f1b --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -33,6 +33,25 @@ class psingle_bank_test(openram_test): debug.info(1, "No column mux") a = bank(c, name="bank1_1rw_0w_0r_single") self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + debug.info(1, "Two way column mux") + a = bank(c, name="bank1_1rw_0w_0r_single") + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + debug.info(1, "Four way column mux") + a = bank(c, name="bank1_1rw_0w_0r_single") + self.local_check(a) + + c.num_words=128 + c.words_per_row=8 + debug.info(1, "Four way column mux") + a = bank(c, name="bank1_1rw_0w_0r_single") + self.local_check(a) + """ # multiport can't generate layout yet on the bank level OPTS.netlist_only = True @@ -120,7 +139,7 @@ class psingle_bank_test(openram_test): self.local_check(a) """ - globals.end_openram() + #globals.end_openram() # instantiate a copy of the class to actually run the test if __name__ == "__main__":