From 583dc4410b7bae2c9b563214850bfb5423838e78 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 22 Feb 2019 16:22:27 -0800
Subject: [PATCH] Revert bus bits back into pins

---
 compiler/characterizer/lib.py                               | 6 +++---
 compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 6 +++---
 .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib     | 6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 9c4e0cf0..00b39af5 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -327,7 +327,7 @@ class lib:
         self.lib.write("        }\n")
         
 
-        self.lib.write("        pin(DOUT{}){{\n".format(read_port))
+        self.lib.write("        pin(DOUT{0}[{1}:0]){{\n".format(read_port,self.sram.word_size-1))
         self.lib.write("        timing(){ \n")
         self.lib.write("            timing_sense : non_unate; \n")
         self.lib.write("            related_pin : \"clk{0}\"; \n".format(read_port))
@@ -360,7 +360,7 @@ class lib:
         self.lib.write("            address : ADDR{0}; \n".format(write_port))
         self.lib.write("            clocked_on  : clk{0}; \n".format(write_port))
         self.lib.write("        }\n") 
-        self.lib.write("        pin(DIN{}){{\n".format(write_port))
+        self.lib.write("        pin(DIN{0}[{1}:0]){{\n".format(write_port,self.sram.word_size-1))
         self.write_FF_setuphold(write_port)
         self.lib.write("        }\n") # pin  
         self.lib.write("    }\n") #bus
@@ -380,7 +380,7 @@ class lib:
         self.lib.write("        direction  : input; \n")
         self.lib.write("        capacitance : {0};  \n".format(tech.spice["dff_in_cap"]))
         self.lib.write("        max_transition       : {0};\n".format(self.slews[-1]))
-        self.lib.write("        pin(ADDR{})".format(port))
+        self.lib.write("        pin(ADDR{0}[{1}:0])".format(port,self.sram.addr_size-1))
         self.lib.write("{\n")
         
         self.write_FF_setuphold(port)
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
index fc8d2be3..0939b4bb 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0){
+        pin(DIN0[1:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0){
+        pin(DOUT0[1:0]){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
         direction  : input; 
         capacitance : 0.2091;  
         max_transition       : 0.04;
-        pin(ADDR0){
+        pin(ADDR0[3:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
index d6fc30aa..f8a337d3 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
@@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
             address : ADDR0; 
             clocked_on  : clk0; 
         }
-        pin(DIN0){
+        pin(DIN0[1:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0"; 
@@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
         memory_read(){ 
             address : ADDR0; 
         }
-        pin(DOUT0){
+        pin(DOUT0[1:0]){
         timing(){ 
             timing_sense : non_unate; 
             related_pin : "clk0"; 
@@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
         direction  : input; 
         capacitance : 9.8242;  
         max_transition       : 0.4;
-        pin(ADDR0){
+        pin(ADDR0[3:0]){
         timing(){ 
             timing_type : setup_rising; 
             related_pin  : "clk0";